hal_integrator.h

开放源码实时操作系统源码.

#define ARM_BAUD_460800                 1
#define ARM_BAUD_230400                 3
#define ARM_BAUD_115200                 7
#define ARM_BAUD_57600                  15
#define ARM_BAUD_38400                  23
#define ARM_BAUD_19200                  47
#define ARM_BAUD_14400                  63
#define ARM_BAUD_9600                   95
#define ARM_BAUD_4800                   191
#define ARM_BAUD_2400                   383
#define ARM_BAUD_1200                   767

// PCI Base area
#define INTEGRATOR_PCI_BASE		0x40000000
#define INTEGRATOR_PCI_SIZE		0x3FFFFFFF

// memory map as seen by the CPU on the local bus
#define CPU_PCI_IO_ADRS		0x60000000 	// PCI I/O space base
#define CPU_PCI_IO_SIZE		0x10000	

#define CPU_PCI_CNFG_ADRS	0x61000000	// PCI config space
#define CPU_PCI_CNFG_SIZE	0x1000000

#define PCI_MEM_BASE            0x40000000   // 512M to xxx
//  unused 256M from A0000000-AFFFFFFF might be used for I2O ???
#define PCI_IO_BASE             0x60000000   // 16M to xxx
//  unused (128-16)M from B1000000-B7FFFFFF
#define PCI_CONFIG_BASE         0x61000000   // 16M to xxx
//  unused ((128-16)M - 64K) from XXX

#define PCI_V3_BASE             0x62000000

// V3 PCI bridge controller
#define V3_BASE			0x62000000    // V360EPC registers

#define V3_PCI_VENDOR           0x00000000
#define V3_PCI_DEVICE           0x00000002
#define V3_PCI_CMD              0x00000004
#define V3_PCI_STAT             0x00000006
#define V3_PCI_CC_REV           0x00000008
#define V3_PCI_HDR_CF           0x0000000C
#define V3_PCI_IO_BASE          0x00000010
#define V3_PCI_BASE0            0x00000014
#define V3_PCI_BASE1            0x00000018
#define V3_PCI_SUB_VENDOR       0x0000002C
#define V3_PCI_SUB_ID           0x0000002E
#define V3_PCI_ROM              0x00000030
#define V3_PCI_BPARAM           0x0000003C
#define V3_PCI_MAP0             0x00000040
#define V3_PCI_MAP1             0x00000044
#define V3_PCI_INT_STAT         0x00000048
#define V3_PCI_INT_CFG          0x0000004C
#define V3_LB_BASE0             0x00000054
#define V3_LB_BASE1             0x00000058
#define V3_LB_MAP0              0x0000005E
#define V3_LB_MAP1              0x00000062
#define V3_LB_BASE2             0x00000064
#define V3_LB_MAP2              0x00000066
#define V3_LB_SIZE              0x00000068
#define V3_LB_IO_BASE           0x0000006E
#define V3_FIFO_CFG             0x00000070
#define V3_FIFO_PRIORITY        0x00000072
#define V3_FIFO_STAT            0x00000074
#define V3_LB_ISTAT             0x00000076
#define V3_LB_IMASK             0x00000077
#define V3_SYSTEM               0x00000078
#define V3_LB_CFG               0x0000007A
#define V3_PCI_CFG              0x0000007C
#define V3_DMA_PCI_ADR0         0x00000080
#define V3_DMA_PCI_ADR1         0x00000090
#define V3_DMA_LOCAL_ADR0       0x00000084
#define V3_DMA_LOCAL_ADR1       0x00000094
#define V3_DMA_LENGTH0          0x00000088
#define V3_DMA_LENGTH1          0x00000098
#define V3_DMA_CSR0             0x0000008B
#define V3_DMA_CSR1             0x0000009B
#define V3_DMA_CTLB_ADR0        0x0000008C
#define V3_DMA_CTLB_ADR1        0x0000009C
#define V3_DMA_DELAY            0x000000E0
#define V3_MAIL_DATA            0x000000C0
#define V3_PCI_MAIL_IEWR        0x000000D0
#define V3_PCI_MAIL_IERD        0x000000D2
#define V3_LB_MAIL_IEWR         0x000000D4
#define V3_LB_MAIL_IERD         0x000000D6
#define V3_MAIL_WR_STAT         0x000000D8
#define V3_MAIL_RD_STAT         0x000000DA
#define V3_QBA_MAP              0x000000DC

// SYSTEM register bits
#define V3_SYSTEM_M_RST_OUT             (1 << 15)
#define V3_SYSTEM_M_LOCK                (1 << 14)

//  PCI_CFG bits
#define V3_PCI_CFG_M_RETRY_EN           (1 << 10)
#define V3_PCI_CFG_M_AD_LOW1            (1 << 9)
#define V3_PCI_CFG_M_AD_LOW0            (1 << 8)

// PCI MAP register bits (PCI -> Local bus)
#define V3_PCI_MAP_M_MAP_ADR            0xFFF00000
#define V3_PCI_MAP_M_RD_POST_INH        (1 << 15)
#define V3_PCI_MAP_M_ROM_SIZE           (1 << 11 | 1 << 10)
#define V3_PCI_MAP_M_SWAP               (1 << 9 | 1 << 8)
#define V3_PCI_MAP_M_ADR_SIZE           0x000000F0
#define V3_PCI_MAP_M_REG_EN             (1 << 1)
#define V3_PCI_MAP_M_ENABLE             (1 << 0)

// 9 => 512M window size
#define V3_PCI_MAP_M_ADR_SIZE_512M      0x00000090

// A => 1024M window size
#define V3_PCI_MAP_M_ADR_SIZE_1024M     0x000000A0

// LB_BASE register bits (Local bus -> PCI)
#define V3_LB_BASE_M_MAP_ADR            0xFFF00000
#define V3_LB_BASE_M_SWAP               (1 << 8 | 1 << 9)
#define V3_LB_BASE_M_ADR_SIZE           0x000000F0
#define V3_LB_BASE_M_PREFETCH           (1 << 3)
#define V3_LB_BASE_M_ENABLE             (1 << 0)

// PCI COMMAND REGISTER bits
#define V3_COMMAND_M_FBB_EN             (1 << 9)
#define V3_COMMAND_M_SERR_EN            (1 << 8)
#define V3_COMMAND_M_PAR_EN             (1 << 6)
#define V3_COMMAND_M_MASTER_EN          (1 << 2)
#define V3_COMMAND_M_MEM_EN             (1 << 1)
#define V3_COMMAND_M_IO_EN              (1 << 0)

#define INTEGRATOR_SC_BASE		0x11000000
#define INTEGRATOR_SC_PCIENABLE_OFFSET	0x18
#define INTEGRATOR_SC_PCIENABLE \
			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)



#define SZ_256M                         0x10000000

// Integrator EBI register definitions

#define INTEGRATOR_EBI_BASE 0x12000000

#define INTEGRATOR_EBI_CSR0_OFFSET      0x00
#define INTEGRATOR_EBI_CSR1_OFFSET      0x04
#define INTEGRATOR_EBI_CSR2_OFFSET      0x08
#define INTEGRATOR_EBI_CSR3_OFFSET      0x0C
#define INTEGRATOR_EBI_LOCK_OFFSET      0x20

#define INTEGRATOR_EBI_CSR0 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR0_OFFSET)
#define INTEGRATOR_EBI_CSR1 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define INTEGRATOR_EBI_CSR2 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR2_OFFSET)
#define INTEGRATOR_EBI_CSR3 (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_CSR3_OFFSET)
#define INTEGRATOR_EBI_LOCK (INTEGRATOR_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)

#define INTEGRATOR_EBI_8_BIT            0x00
#define INTEGRATOR_EBI_16_BIT           0x01
#define INTEGRATOR_EBI_32_BIT           0x02
#define INTEGRATOR_EBI_WRITE_ENABLE     0x04
#define INTEGRATOR_EBI_SYNC             0x08
#define INTEGRATOR_EBI_WS_2             0x00
#define INTEGRATOR_EBI_WS_3             0x10
#define INTEGRATOR_EBI_WS_4             0x20
#define INTEGRATOR_EBI_WS_5             0x30
#define INTEGRATOR_EBI_WS_6             0x40
#define INTEGRATOR_EBI_WS_7             0x50
#define INTEGRATOR_EBI_WS_8             0x60
#define INTEGRATOR_EBI_WS_9             0x70
#define INTEGRATOR_EBI_WS_10            0x80
#define INTEGRATOR_EBI_WS_11            0x90
#define INTEGRATOR_EBI_WS_12            0xA0
#define INTEGRATOR_EBI_WS_13            0xB0
#define INTEGRATOR_EBI_WS_14            0xC0
#define INTEGRATOR_EBI_WS_15            0xD0
#define INTEGRATOR_EBI_WS_16            0xE0
#define INTEGRATOR_EBI_WS_17            0xF0

#define FL_SC_CONTROL			0x06	// Enable Flash Write and Vpp

/* 
 *  System Controller
 * 
 */
#define INTEGRATOR_SC_ID_OFFSET         0x00
#define INTEGRATOR_SC_OSC_OFFSET        0x04
#define INTEGRATOR_SC_CTRLS_OFFSET      0x08
#define INTEGRATOR_SC_CTRLC_OFFSET      0x0C
#define INTEGRATOR_SC_DEC_OFFSET        0x10
#define INTEGRATOR_SC_ARB_OFFSET        0x14
#define INTEGRATOR_SC_PCIENABLE_OFFSET  0x18
#define INTEGRATOR_SC_LOCK_OFFSET       0x1C

#define INTEGRATOR_SC_BASE              0x11000000
#define INTEGRATOR_SC_ID                (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ID_OFFSET)
#define INTEGRATOR_SC_OSC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_OSC_OFFSET)
#define INTEGRATOR_SC_CTRLS             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLS_OFFSET)
#define INTEGRATOR_SC_CTRLC             (INTEGRATOR_SC_BASE + INTEGRATOR_SC_CTRLC_OFFSET)
#define INTEGRATOR_SC_DEC               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_DEC_OFFSET)
#define INTEGRATOR_SC_ARB               (INTEGRATOR_SC_BASE + INTEGRATOR_SC_ARB_OFFSET)
#define INTEGRATOR_SC_PCIENABLE         (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
#define INTEGRATOR_SC_LOCK              (INTEGRATOR_SC_BASE + INTEGRATOR_SC_LOCK_OFFSET)

#endif //CYGONCE_HAL_INTEGRATOR_H