hal_integrator.h

开放源码实时操作系统源码.

#ifndef CYGONCE_HAL_INTEGRATOR_H
#define CYGONCE_HAL_INTEGRATOR_H

/*=============================================================================
//
//      hal_integrator.h
//
//      HAL Description of INTEGRATOR board
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Philippe Robin
// Contributors: 
// Date:         November 7, 2000
// Purpose:      
// Description:
// Usage:        #include <cyg/hal/hal_integrator.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================*/


#define INTEGRATOR_HDR_BASE             0x10000000
#define INTEGRATOR_HDR_CTRL_OFFSET      0x0C
#define INTEGRATOR_HDR_CTRL_REMAP       0x04

#define INTEGRATOR_BOOT_ROM_BASE	0x20000000
#define INTEGRATOR_HDR0_SDRAM_BASE      0x80000000

#define INTEGRATOR_DBG_ALPHA_OFFSET     0x00
#define INTEGRATOR_DBG_LEDS_OFFSET      0x04
#define INTEGRATOR_DBG_SWITCH_OFFSET    0x08

#define INTEGRATOR_DBG_BASE             0x1A000000
#define INTEGRATOR_DBG_ALPHA            (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_ALPHA_OFFSET)
#define INTEGRATOR_DBG_LEDS             (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_LEDS_OFFSET)
#define INTEGRATOR_DBG_SWITCH           (INTEGRATOR_DBG_BASE + INTEGRATOR_DBG_SWITCH_OFFSET)

#define INTEGRATOR_UART0_BASE                   0x16000000	 /*  UART 0 */
#define INTEGRATOR_UART1_BASE                   0x17000000	 /*  UART 1 */

#define INTEGRATOR_IRQCONT_BASE              	0x14000000

#define INTEGRATOR_IRQSTATUS			0x00
#define INTEGRATOR_IRQRAWSTATUS		 	0x04
#define INTEGRATOR_IRQENABLE			0x08
#define INTEGRATOR_IRQENABLESET	        	0x08
#define INTEGRATOR_IRQENABLECLEAR		0x0C

#define INTEGRATOR_IRQSOFT			0x10
#define INTEGRATOR_IRQSOFTSET		        0x10
#define INTEGRATOR_IRQSOFTCLEAR		        0x14

#define INTEGRATOR_FIQSTATUS			0x20
#define INTEGRATOR_FIQRAWSTATUS			0x24
#define INTEGRATOR_FIQENABLE			0x28
#define INTEGRATOR_FIQENABLESET			0x28
#define INTEGRATOR_FIQENABLECLEAR		0x2C

#define INTEGRATOR_IRQCONT_IRQSTATUS		(INTEGRATOR_IRQCONT_BASE + INTEGRATOR_IRQSTATUS)
#define INTEGRATOR_IRQCONT_IRQRAWSTATUS         (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_IRQRAWSTATUS)
#define INTEGRATOR_IRQCONT_IRQENABLE            (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_IRQENABLE)
#define INTEGRATOR_IRQCONT_IRQENABLESET         (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_IRQENABLESET)
#define INTEGRATOR_IRQCONT_IRQENABLECLEAR       (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_IRQENABLECLEAR)
#define INTEGRATOR_IRQCONT_IRQSOFT              (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_IRQSOFT)
#define INTEGRATOR_IRQCONT_IRQSOFTSET           (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_IRQSOFTSET)
#define INTEGRATOR_IRQCONT_IRQSOFTCLEAR         (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_IRQSOFTCLEAR)
#define INTEGRATOR_IRQCONT_FIQSTATUS            (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_FIQSTATUS)
#define INTEGRATOR_IRQCONT_FIQRAWSTATUS         (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_FIQRAWSTATUS)
#define INTEGRATOR_IRQCONT_FIQENABLE            (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_FIQENABLE)
#define INTEGRATOR_IRQCONT_FIQENABLESET         (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_FIQENABLESET)
#define INTEGRATOR_IRQCONT_FIQENABLECLEAR       (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_FIQENABLECLEAR)
#define INTEGRATOR_IRQCONT_FIQSOFT              (INTEGRATOR_IRQCONT_BASE + INTEGRATOR_FIQSOFT)

// Interrupt controller registers
#define CYG_DEVICE_ICTL_BASE            INTEGRATOR_IRQCONT_BASE
#define CYG_DEVICE_IRQ_Status \
    ((volatile cyg_uint32 *) (CYG_DEVICE_ICTL_BASE + INTEGRATOR_IRQSTATUS))
    // Current status, read only
#define CYG_DEVICE_IRQ_Enable \
    ((volatile cyg_uint32 *) (CYG_DEVICE_ICTL_BASE + INTEGRATOR_IRQENABLE))
    // Enable status, read only
#define CYG_DEVICE_IRQ_EnableSet \
    ((volatile cyg_uint32 *) (CYG_DEVICE_ICTL_BASE + INTEGRATOR_IRQENABLESET))
    // Enable (1's only), write only
#define CYG_DEVICE_IRQ_EnableClear \
    ((volatile cyg_uint32 *) (CYG_DEVICE_ICTL_BASE + INTEGRATOR_IRQENABLECLEAR))
    // Disable (1's only), write only

// Timer registers
#define INTEGRATOR_CT_BASE              0x13000000	 /*  Counter/Timers */

#define INTEGRATOR_TIMER0_BASE          INTEGRATOR_CT_BASE
#define INTEGRATOR_TIMER1_BASE          (INTEGRATOR_CT_BASE + 0x100)
#define INTEGRATOR_TIMER2_BASE          (INTEGRATOR_CT_BASE + 0x200)

#define CYG_DEVICE_TIMER_BASE           INTEGRATOR_TIMER2_BASE

#define CYG_DEVICE_TIMER_LOAD \
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER_BASE + 0x00))
    // Load value, read/write
#define CYG_DEVICE_TIMER_CURRENT \
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER_BASE + 0x04))
    // Current value, read
#define CYG_DEVICE_TIMER_CONTROL \
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER_BASE + 0x08))
    // Control register, read/write
#define CYG_DEVICE_TIMER_CLEAR \
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER_BASE + 0x0C))
    // Clears interrrupt, write only

// Clock/timer control register
#define CTL_ENABLE      0x80            // Bit   7: 1 - counter enabled
#define CTL_DISABLE     0x00            //          0 - counter disabled
#define CTL_FREERUN     0x00            // Bit   6: 0 - free running counter
#define CTL_PERIODIC    0x40            //          1 - periodic timer mode
#define CTL_SCALE_1     0x00            // Bits 32: 00 - Scale clock by 1
#define CTL_SCALE_16    0x04            //          01 - Scale by 16
#define CTL_SCALE_256   0x08            //          10 - Scale by 256
                                        //               12.8us/tick
/*-------------------------------------------------------------------------------
 *  From AMBA UART (PL010) Block Specification (ARM-0001-CUST-DSPC-A03)
 * -------------------------------------------------------------------------------
 *  UART Register Offsets.
 */
#define AMBA_UARTDR                     0x00	 /*  Data read or written from the interface. */
#define AMBA_UARTRSR                    0x04	 /*  Receive status register (Read). */
#define AMBA_UARTECR                    0x04	 /*  Error clear register (Write). */
#define AMBA_UARTLCR_H                  0x08	 /*  Line control register, high byte. */
#define AMBA_UARTLCR_M                  0x0C	 /*  Line control register, middle byte. */
#define AMBA_UARTLCR_L                  0x10	 /*  Line control register, low byte. */
#define AMBA_UARTCR                     0x14	 /*  Control register. */
#define AMBA_UARTFR                     0x18	 /*  Flag register (Read only). */
#define AMBA_UARTIIR                    0x1C	 /*  Interrupt indentification register (Read). */
#define AMBA_UARTICR                    0x1C	 /*  Interrupt clear register (Write). */
#define AMBA_UARTILPR                   0x20	 /*  IrDA low power counter register. */

#define AMBA_UARTRSR_OE                 0x08
#define AMBA_UARTRSR_BE                 0x04
#define AMBA_UARTRSR_PE                 0x02
#define AMBA_UARTRSR_FE                 0x01

#define AMBA_UARTFR_TXFF                0x20
#define AMBA_UARTFR_RXFE                0x10
#define AMBA_UARTFR_BUSY                0x08
#define AMBA_UARTFR_TMSK                (AMBA_UARTFR_TXFF + AMBA_UARTFR_BUSY)
 
#define AMBA_UARTCR_RTIE                0x40
#define AMBA_UARTCR_TIE                 0x20
#define AMBA_UARTCR_RIE                 0x10
#define AMBA_UARTCR_MSIE                0x08
#define AMBA_UARTCR_IIRLP               0x04
#define AMBA_UARTCR_SIREN               0x02
#define AMBA_UARTCR_UARTEN              0x01
 
#define AMBA_UARTLCR_H_WLEN_8           0x60
#define AMBA_UARTLCR_H_WLEN_7           0x40
#define AMBA_UARTLCR_H_WLEN_6           0x20
#define AMBA_UARTLCR_H_WLEN_5           0x00
#define AMBA_UARTLCR_H_FEN              0x10
#define AMBA_UARTLCR_H_STP2             0x08
#define AMBA_UARTLCR_H_EPS              0x04
#define AMBA_UARTLCR_H_PEN              0x02
#define AMBA_UARTLCR_H_BRK              0x01

#define AMBA_UARTIIR_RTIS               0x08
#define AMBA_UARTIIR_TIS                0x04
#define AMBA_UARTIIR_RIS                0x02
#define AMBA_UARTIIR_MIS                0x01