📄 pci_bios.h
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//=============================================================================
//
// pci_bios.h - Cyclone Diagnostics
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): Scott Coulter, Jeff Frazier, Eric Breeden
// Contributors:
// Date: 2001-01-25
// Purpose:
// Description:
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
/****************************************************************************/
/* File: pci_bios.h */
/* */
/* Use: mon960 */
/* */
/* Purpose: PCI BIOS Routines */
/* */
/* Remarks: Conforming to the Revision 2.1 PCI BIOS Specfication */
/* */
/* Functions Supported: */
/* */
/* pci_bios_present() */
/* find_pci_device() */
/* find_pci_class_code() */
/* generate_special_cycle() */
/* read_config_byte() */
/* read_config_word() */
/* read_config_dword() */
/* write_config_byte() */
/* write_config_word() */
/* write_config_dword() */
/* get_irq_routing_options() */
/* set_pci_irq() */
/* */
/* History: */
/* 06Sep00 Scott Coulter Changed NUM_PCI_BUSES from 31 to 2 */
/* 09Sep97 Jim Otto Defined NUM_PCI_BUSES */
/* */
/* */
/* */
/****************************************************************************/
#include "iq80310.h"
#define XINT0 0
#define XINT1 1
#define XINT2 2
#define XINT3 3
/* primary PCI bus definitions */
#define PRIMARY_BUS_NUM 0
#define PRIMARY_MEM_BASE 0x80000000
#define PRIMARY_DAC_BASE 0x84000000
#define PRIMARY_IO_BASE 0x90000000
#define PRIMARY_MEM_LIMIT 0x83ffffff
#define PRIMARY_DAC_LIMIT 0x87ffffff
#define PRIMARY_IO_LIMIT 0x9000ffff
/* secondary PCI bus definitions */
#define SECONDARY_BUS_NUM 1
#define SECONDARY_MEM_BASE 0x88000000
#define SECONDARY_DAC_BASE 0x8c000000
#define SECONDARY_IO_BASE 0x90010000
#define SECONDARY_MEM_LIMIT 0x8bffffff
#define SECONDARY_DAC_LIMIT 0x8fffffff
#define SECONDARY_IO_LIMIT 0x9001ffff
#define LAST_SYSPROC 260
#define NUM_PCI_BUSES 2
#ifndef ASM_LANGUAGE
/******************************************************************************
*
* Required PCI BIOS Data Structures
*
*/
typedef struct
{
int num_devices;
int num_functions;
} PCI_DATA;
typedef struct
{
int present_status; /* set to 0x00 for BIOS present */
int hardware_mech_config; /* for accessing config. space */
int hardware_mech_special; /* for performing special cycles */
int if_level_major_ver; /* in BCD, 0x02 for version 2.1 */
int if_level_minor_ver; /* in BCD, 0x01 for version 2.1 */
int last_pci_bus; /* numbers start at 0 */
} PCI_BIOS_INFO;
/*******************************************************************************
*
* Type 0 PCI Configuration Space Header
*
*/
typedef struct
{
unsigned short vendor_id;
unsigned short device_id;
unsigned short command;
unsigned short status;
unsigned char revision_id;
unsigned char prog_if;
unsigned char sub_class;
unsigned char base_class;
unsigned char cache_line_size;
unsigned char latency_timer;
unsigned char header_type;
unsigned char bist;
unsigned long pcibase_addr0;
unsigned long pcibase_addr1;
unsigned long pcibase_addr2;
unsigned long pcibase_addr3;
unsigned long pcibase_addr4;
unsigned long pcibase_addr5;
unsigned long cardbus_cis_ptr;
unsigned short sub_vendor_id;
unsigned short sub_device_id;
unsigned long pcibase_exp_rom;
unsigned long reserved2[2];
unsigned char int_line;
unsigned char int_pin;
unsigned char min_gnt;
unsigned char max_lat;
} PCI_CONFIG_SPACE_0;
/*******************************************************************************
*
* PCI Bridge Configuration Space Header
*
*/
typedef struct
{
unsigned short vendor_id;
unsigned short device_id;
unsigned short command;
unsigned short status;
unsigned char revision_id;
unsigned char prog_if;
unsigned char sub_class;
unsigned char base_class;
unsigned char cache_line_size;
unsigned char latency_timer;
unsigned char header_type;
unsigned char bist;
unsigned long pcibase_addr0;
unsigned long pcibase_addr1;
unsigned char primary_busno;
unsigned char secondary_busno;
unsigned char subordinate_busno;
unsigned char secondary_latency_timer;
unsigned char io_base;
unsigned char io_limit;
unsigned short secondary_status;
unsigned short mem_base;
unsigned short mem_limit;
unsigned short pfmem_base;
unsigned short pfmem_limit;
unsigned long pfbase_upper32;
unsigned long pflimit_upper32;
unsigned short iobase_upper16;
unsigned short iolimit_upper16;
unsigned short sub_vendor_id;
unsigned short sub_device_id;
unsigned long pcibase_exp_rom;
unsigned char int_line;
unsigned char int_pin;
unsigned short bridge_control;
} PCI_CONFIG_SPACE_1;
typedef union
{
PCI_CONFIG_SPACE_0 pci0_config;
PCI_CONFIG_SPACE_1 pci1_config;
} PCI_CONFIG_SPACE;
#define CONFIG_MECHANISM_1 1
#define CONFIG_MECHANISM_2 2
typedef struct
{
int bus_number; /* 0...255 */
int device_number; /* Device number on bus */
int function_number; /* Function number on device */
} PCI_DEVICE_LOCATION;
typedef struct
{
int bus_number; /* 0...255 */
int device_number; /* Device number on bus */
int inta_link; /* Which ints. are or'd together */
int inta_bitmap; /* Which XINT connected to */
int intb_link; /* Which ints. are or'd together */
int intb_bitmap; /* Which XINT connected to */
int intc_link; /* Which ints. are or'd together */
int intc_bitmap; /* Which XINT connected to */
int intd_link; /* Which ints. are or'd together */
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