hal_pxa2x0.h

开放源码实时操作系统源码.

//==========================================================================
//
//      hal_pxa2x0.h
//
//      HAL misc board support definitions for PXA250/210
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
// Copyright (C) 2003 Gary Thomas
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    <[e-mail]>
// Date:         2003-01-06
//
//####DESCRIPTIONEND####
//
//==========================================================================
#ifndef CYGONCE_HAL_ARM_PXA2X0_H
#define CYGONCE_HAL_ARM_PXA2X0_H

#include <pkgconf/system.h>
#include <cyg/hal/hal_xscale.h>

#ifdef __ASSEMBLER__
#define PXA2X0_REGISTER(a)	(a)
#else
#define PXA2X0_REGISTER(a)	((volatile unsigned long *)(a))
#endif

// Memory layout
#define PXA2X0_CS0_BASE				(0x00000000)
#define PXA2X0_CS1_BASE				(0x04000000)
#define PXA2X0_CS2_BASE				(0x08000000)
#define PXA2X0_CS3_BASE				(0x0c000000)
#define PXA2X0_CS4_BASE				(0x10000000)
#define PXA2X0_CS5_BASE				(0x14000000)

#define PXA2X0_PCMCIA0_BASE			(0x20000000)
#define PXA2X0_PCMCIA1_BASE			(0x30000000)

#define PXA2X0_PERIPHERALS_BASE		(0x40000000)
#define PXA2X0_LCD_BASE				(0x44000000)
#define PXA2X0_MEMORY_CTL_BASE		(0x48000000)

#define PXA2X0_RAM_BANK0_BASE		(0xA0000000)
#define PXA2X0_RAM_BANK1_BASE		(0xA4000000)
#define PXA2X0_RAM_BANK2_BASE		(0xA8000000)
#define PXA2X0_RAM_BANK3_BASE		(0xAc000000)

#define PXA2X0_CACHE_FLUSH_BASE		(0xc0000000)

#define DCACHE_FLUSH_AREA			0xc0000000

// DMA Controller
#define PXA2X0_DMA_CTL_BASE			( PXA2X0_PERIPHERALS_BASE + 0x0000000 )
#define PXA2X0_DCSR0				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0000 )
#define PXA2X0_DCSR1				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0004 )
#define PXA2X0_DCSR2				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0008 )
#define PXA2X0_DCSR3				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x000c )
#define PXA2X0_DCSR4				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0010 )
#define PXA2X0_DCSR5				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0014 )
#define PXA2X0_DCSR6				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0018 )
#define PXA2X0_DCSR7				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x001c )
#define PXA2X0_DCSR8				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0020 )
#define PXA2X0_DCSR9				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0024 )
#define PXA2X0_DCSR10				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0028 )
#define PXA2X0_DCSR11				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x002c )
#define PXA2X0_DCSR12				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0030 )
#define PXA2X0_DCSR13				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0034 )
#define PXA2X0_DCSR14				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0038 )
#define PXA2X0_DCSR15				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x003c )
#define PXA2X0_DINT					PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x00f0 )
#define PXA2X0_DRCMR0				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0100 )
#define PXA2X0_DRCMR1				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0104 )
#define PXA2X0_DRCMR2				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0108 )
#define PXA2X0_DRCMR3				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x010c )
#define PXA2X0_DRCMR4				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0110 )
#define PXA2X0_DRCMR5				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0114 )
#define PXA2X0_DRCMR6				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0118 )
#define PXA2X0_DRCMR7				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x011c )
#define PXA2X0_DRCMR8				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0120 )
#define PXA2X0_DRCMR9				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0124 )
#define PXA2X0_DRCMR10				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0128 )
#define PXA2X0_DRCMR11				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x012c )
#define PXA2X0_DRCMR12				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0130 )
#define PXA2X0_DRCMR13				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0134 )
#define PXA2X0_DRCMR14				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0138 )
#define PXA2X0_DRCMR15				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x013c )
#define PXA2X0_DRCMR16				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0140 )
#define PXA2X0_DRCMR17				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0144 )
#define PXA2X0_DRCMR18				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0148 )
#define PXA2X0_DRCMR19				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x014c )
#define PXA2X0_DRCMR20				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0150 )
#define PXA2X0_DRCMR21				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0154 )
#define PXA2X0_DRCMR22				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0158 )
#define PXA2X0_DRCMR23				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x015c )
#define PXA2X0_DRCMR24				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0160 )
#define PXA2X0_DRCMR25				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0164 )
#define PXA2X0_DRCMR26				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0168 )
#define PXA2X0_DRCMR27				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x016c )
#define PXA2X0_DRCMR28				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0170 )
#define PXA2X0_DRCMR29				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0174 )
#define PXA2X0_DRCMR30				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0178 )
#define PXA2X0_DRCMR31				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x017c )
#define PXA2X0_DRCMR32				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0180 )
#define PXA2X0_DRCMR33				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0184 )
#define PXA2X0_DRCMR34				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0188 )
#define PXA2X0_DRCMR35				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x018c )
#define PXA2X0_DRCMR36				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0190 )
#define PXA2X0_DRCMR37				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0194 )
#define PXA2X0_DRCMR38				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0198 )
#define PXA2X0_DRCMR39				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x019c )
#define PXA2X0_DDADR0				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0200 )
#define PXA2X0_DSADR0				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0204 )
#define PXA2X0_DTADR0				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0208 )
#define PXA2X0_DCMD0				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x020c )
#define PXA2X0_DDADR1				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0210 )
#define PXA2X0_DSADR1				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0214 )
#define PXA2X0_DTADR1				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0218 )
#define PXA2X0_DCMD1				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x021c )
#define PXA2X0_DDADR2				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0220 )
#define PXA2X0_DSADR2				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0224 )
#define PXA2X0_DTADR2				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0228 )
#define PXA2X0_DCMD2				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x022c )
#define PXA2X0_DDADR3				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0230 )
#define PXA2X0_DSADR3				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0234 )
#define PXA2X0_DTADR3				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0238 )
#define PXA2X0_DCMD3				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x023c )
#define PXA2X0_DDADR4				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0240 )
#define PXA2X0_DSADR4				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0244 )
#define PXA2X0_DTADR4				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0248 )
#define PXA2X0_DCMD4				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x024c )
#define PXA2X0_DDADR5				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0250 )
#define PXA2X0_DSADR5				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0254 )
#define PXA2X0_DTADR5				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0258 )
#define PXA2X0_DCMD5				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x025c )
#define PXA2X0_DDADR6				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0260 )
#define PXA2X0_DSADR6				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0264 )
#define PXA2X0_DTADR6				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0268 )
#define PXA2X0_DCMD6				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x026c )
#define PXA2X0_DDADR7				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0270 )
#define PXA2X0_DSADR7				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0274 )
#define PXA2X0_DTADR7				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0278 )
#define PXA2X0_DCMD7				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x027c )
#define PXA2X0_DDADR8				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0280 )
#define PXA2X0_DSADR8				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0284 )
#define PXA2X0_DTADR8				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0288 )
#define PXA2X0_DCMD8				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x028c )
#define PXA2X0_DDADR9				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0290 )
#define PXA2X0_DSADR9				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0294 )
#define PXA2X0_DTADR9				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x0298 )
#define PXA2X0_DCMD9				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x029c )
#define PXA2X0_DDADR10				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a0 )
#define PXA2X0_DSADR10				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a4 )
#define PXA2X0_DTADR10				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02a8 )
#define PXA2X0_DCMD10				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02ac )
#define PXA2X0_DDADR11				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b0 )
#define PXA2X0_DSADR11				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b4 )
#define PXA2X0_DTADR11				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02b8 )
#define PXA2X0_DCMD11				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02bc )
#define PXA2X0_DDADR12				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c0 )
#define PXA2X0_DSADR12				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c4 )
#define PXA2X0_DTADR12				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02c8 )
#define PXA2X0_DCMD12				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02cc )
#define PXA2X0_DDADR13				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d0 )
#define PXA2X0_DSADR13				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d4 )
#define PXA2X0_DTADR13				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02d8 )
#define PXA2X0_DCMD13				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02dc )
#define PXA2X0_DDADR14				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e0 )
#define PXA2X0_DSADR14				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e4 )
#define PXA2X0_DTADR14				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02e8 )
#define PXA2X0_DCMD14				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02ec )
#define PXA2X0_DDADR15				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f0 )
#define PXA2X0_DSADR15				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f4 )
#define PXA2X0_DTADR15				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02f8 )
#define PXA2X0_DCMD15				PXA2X0_REGISTER( PXA2X0_DMA_CTL_BASE+0x02fc )

// Full Function UART
#define PXA2X0_FFUART_BASE			( PXA2X0_PERIPHERALS_BASE + 0x0100000 )
#define PXA2X0_FFRBR				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 )
#define PXA2X0_FFTHR				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0000 )
#define PXA2X0_FFIER				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0004 )
#define PXA2X0_FFIIR				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0008 )
#define PXA2X0_FFFCR				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0008 )
#define PXA2X0_FFLCR				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x000c )
#define PXA2X0_FFMCR				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0010 )
#define PXA2X0_FFLSR				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0014 )
#define PXA2X0_FFMSR				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x0018 )
#define PXA2X0_FFSPR				PXA2X0_REGISTER( PXA2X0_FFUART_BASE+0x001c )