📄 hal_cache.h
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"mrc p15,0,r1,c1,c0,0;" /* disable cache */ \
"bic r1,r1,#4;" \
"mcr p15,0,r1,c1,c0,0;" \
"mrc p15,0,r1,c1,c0,1;" /* disable coalescing */ \
"orr r1,r1,#1;" \
"mcr p15,0,r1,c1,c0,1;" \
"mcr p15,0,r1,c7,c6,0;" /* invalidate data cache */ \
/* cpuwait */ \
"mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
"mov r1,r1;" \
"sub pc,pc,#4;" \
: \
: \
: "r1" /* Clobber list */ \
); \
CYG_MACRO_END
// Query the state of the data cache
#define HAL_DCACHE_IS_ENABLED(_state_) \
CYG_MACRO_START \
register int reg; \
asm volatile ("mrc p15,0,%0,c1,c0,0" \
: "=r"(reg) \
: \
/*:*/ \
); \
(_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
CYG_MACRO_END
// Flush the entire dcache (and then both TLBs, just in case)
#define HAL_DCACHE_INVALIDATE_ALL() \
CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
/* this macro can discard dirty cache lines. */ \
asm volatile ( \
"mcr p15,0,r1,c7,c6,0;" /* invalidate data cache */ \
"mcr p15,0,r1,c8,c7,0;" /* flush I+D TLBs */ \
: \
: \
: "r1" /* Clobber list */ \
); \
CYG_MACRO_END
// DCACHE_FLUSH_AREA is defined if writeback caching is used. Otherwise
// write-through is assumed.
#ifdef DCACHE_FLUSH_AREA
// Evict dirty lines from write-back caches
#define HAL_DCACHE_EVICT() \
CYG_MACRO_START \
/* The best way to evict a dirty line is by using the */ \
/* line allocate operation on non-existent memory. */ \
asm volatile ( \
"mov r0, %0;" /* cache flush region */ \
"add r1, r0, #0x8800;" /* 32KB main + 2KB mini cache */ \
"667: " \
"mcr p15,0,r0,c7,c2,5;" /* allocate a line */ \
"add r0, r0, #32;" /* 32 bytes/line */ \
"teq r1, r0;" \
"bne 667b;" \
: \
: "i" (DCACHE_FLUSH_AREA) \
: "r0","r1" /* Clobber list */ \
); \
CYG_MACRO_END
#else
#define HAL_DCACHE_EVICT()
#endif
// Synchronize the contents of the cache with memory.
#define HAL_DCACHE_SYNC() \
CYG_MACRO_START \
HAL_DCACHE_EVICT(); \
asm volatile ( \
"mcr p15,0,r0,c7,c6,0;" /* invalidate data cache */ \
/* cpuwait */ \
"mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
"mov r1,r1;" \
"sub pc,pc,#4;" \
"mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
/* cpuwait */ \
"mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
"mov r1,r1;" \
"sub pc,pc,#4;" \
"nop" \
: \
: \
: "r0","r1" /* Clobber list */ \
); \
CYG_MACRO_END
// Set the data cache refill burst size
//#define HAL_DCACHE_BURST_SIZE(_size_)
// This feature is not available on the XScale.
// Set the data cache write mode
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
// This feature is not available on the XScale.
#define HAL_DCACHE_WRITETHRU_MODE 0
#define HAL_DCACHE_WRITEBACK_MODE 1
// Get the current writeback mode - or only writeback mode if fixed
#ifdef DCACHE_FLUSH_AREA
#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
_mode_ = HAL_DCACHE_WRITEBACK_MODE; \
CYG_MACRO_END
#else
#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
_mode_ = HAL_DCACHE_WRITETHRU_MODE; \
CYG_MACRO_END
#endif
// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
//#define HAL_DCACHE_LOCK(_base_, _size_)
// This feature is not available on the XScale.
// Undo a previous lock operation
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
// This feature is not available on the XScale.
// Unlock entire cache
//#define HAL_DCACHE_UNLOCK_ALL()
// This feature is not available on the XScale.
//-----------------------------------------------------------------------------
// Data cache line control
// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
// This feature is not available on the XScale.
// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
CYG_MACRO_START \
HAL_DCACHE_STORE( _base_ , _size_ ); \
HAL_DCACHE_INVALIDATE( _base_ , _size_ ); \
CYG_MACRO_END
// Invalidate cache lines in the given range without writing to memory.
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
CYG_MACRO_START \
register int addr, enda; \
for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_), \
enda = (int)(_base_) + (_size_); \
addr < enda ; \
addr += HAL_DCACHE_LINE_SIZE ) \
{ \
asm volatile ( \
"mcr p15,0,%0,c7,c6,1;" /* flush entry away */ \
: \
: "r"(addr) \
: "memory" \
); \
} \
CYG_MACRO_END
// Write dirty cache lines to memory for the given address range.
#define HAL_DCACHE_STORE( _base_ , _size_ ) \
CYG_MACRO_START \
register int addr, enda; \
for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_), \
enda = (int)(_base_) + (_size_); \
addr < enda ; \
addr += HAL_DCACHE_LINE_SIZE ) \
{ \
asm volatile ("mcr p15,0,%0,c7,c10,1;" /* push entry to RAM */ \
: \
: "r"(addr) \
: "memory" \
); \
} \
/* and also drain the write buffer */ \
asm volatile ( \
"mov r1,#0;" \
"mcr p15,0,r1,c7,c10,4;" \
: \
: \
: "r1", "memory" /* Clobber list */ \
); \
CYG_MACRO_END
// Preread the given range into the cache with the intention of reading
// from it later.
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
// This feature is available on the XScale, but due to tricky
// coherency issues with the read buffer (see XScale developer's
// manual) we don't bother to implement it here.
// Preread the given range into the cache with the intention of writing
// to it later.
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
// This feature is not available on the XScale.
// Allocate and zero the cache lines associated with the given range.
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
// This feature is not available on the XScale.
//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_CACHE_H
// End of hal_cache.h
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