📄 hal_platform_setup.h
字号:
// Step 7
ldr r2, =PXA2X0_RAM_BANK0_BASE
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
str r2, [r2]
// Step 8
//
// Step 9
// SDRAM enable
//ldr r3, =MDCNFG_VAL
adr r3, mpc50_static_info
ldr r3, [r3, #MPC50_VAL_OFFS_MDCNFG]
ldr r2, =0x00030003
and r2, r3, r2
ldr r1, =PXA2X0_MEMORY_CTL_BASE
ldr r3, [r1, #MDCNFG_OFFS]
orr r3, r3, r2
str r3, [r1, #MDCNFG_OFFS]
// Step 10
ldr r2, =MDMRS_VAL
str r2, [r1, #MDMRS_OFFS]
.endm
/**********************************************************************************************************************
* GPIOs
**********************************************************************************************************************/
// GPIO Name Pin GPDR GAFR GPSR
// 0 INT0 L10 0 00 0
// 1 INT1 L12 0 00 0
// 2 FLX-CLK L13 1 00 0
// 3 FLX-DAT K14 1 00 0
// 4 FLX-CONFIG J12 1 00 1
// 5 FLX-STATUS J11 0 00 0
// 6 FLX-CONFDONE H14 0 00 0
// 7 LAN_INT G15 0 00 0
// 8 USB-H-ON F14 1 00 1
// 9 USB-CL-ON F12 0 00 0
// 10 MPSB-INT0 F7 0 00 0
// 11 - A7 0 00 0
// 12 MPSB-INT1 B6 0 00 0
// 13 MBGNT B5 1 10 0
// 14 MBREQ B4 0 01 0
// 15 nCS_1 T8 1 10 1
#define GAFR0_L_VAL 0x80000000 //0x98000000
// 16 PWM0 E12 0 00 0
// 17 PWM1 D12 0 00 0
// 18 RDY C1 0 01 0
// 19 DREQ[1] N14 0 00 0
// 20 DREQ[0] N12 0 00 0
// 21 DVAL0 N15 0 00 0
// 22 DVAL1 M12 0 00 0
// 23 SSPSCLK F9 0 00 0
// 24 SSPSFRM E9 0 00 0
// 25 SSPTXD D9 0 00 0
// 26 SSPRXD A9 0 00 0
// 27 SSPEXTCLK B9 0 00 0
// 28 BITCLK C9 0 00 0
// 29 SDATIN0 E10 0 00 0
// 30 SDATOUT A10 0 00 0
// 31 SYNC E11 0 00 0
#define GPDR0_VAL 0x0000811c //0x0000a11c
#define GAFR0_U_VAL 0x00000010
#define GPSR0_VAL 0x00008110
// 32 SDATIN1 A16 0 00 0
// 33 Reset-Button T13 0 00 0
// 34 FFRXD A13 0 01 0
// 35 FFCTS A14 0 01 0
// 36 FFDCD A12 0 01 0
// 37 FFDSR B11 0 01 0
// 38 FFRI B10 0 01 0
// 39 FFTXD E13 1 10 1
// 40 FFDTR F10 1 10 1
// 41 FFRTS F8 1 10 1
// 42 BTRXD B13 0 00 0
// 43 BTTXD D13 0 00 0
// 44 BTCTS A15 0 00 0
// 45 BTRTS B14 0 00 0
// 46 IRRXD B15 0 00 0
// 47 IRTXD C15 0 00 0
#define GAFR1_L_VAL 0x000a9550
// 48 LED_DP P13 1 00 0
// 49 LED_G T14 1 00 0
// 50 LED_F T15 1 00 0
// 51 LED_E R15 1 00 0
// 52 LED_D P14 1 00 0
// 53 LED_C R16 1 00 0
// 54 LED_B P16 1 00 0
// 55 LED_A M13 1 00 0
// 56 GPIO56 N16 0 00 0
// 57 GPIO57 M16 0 00 0
// 58 LCDD0 E7 0 00 0
// 59 LCDD1 D7 0 00 0
// 60 LCDD2 C7 0 00 0
// 61 LCDD3 B7 0 00 0
// 62 LCDD4 E6 0 00 0
// 63 LCDD5 D6 0 00 0
#define GPDR1_VAL 0x00ff0380
#define GAFR1_U_VAL 0x00000000
#define GPSR1_VAL 0x00000380
#define GPSR_LED_VAL 0x00ff0000
// 64 LCDD6 E5 0 00 0
// 65 LCDD7 A6 0 00 0
// 66 LCDD8 C5 0 00 0
// 67 LCDD9 A5 0 00 0
// 68 LCDD10 D5 0 00 0
// 69 LCDD11 A4 0 00 0
// 70 LCDD12 A3 0 00 0
// 71 LCDD13 A2 0 00 0
// 72 LCDD14 C3 0 00 0
// 73 LCDD15 B3 0 00 0
// 74 LCDFCLK E8 0 00 0
// 75 LCDLCLK D8 0 00 0
// 76 LCDPCLK B8 0 00 0
// 77 LCDBIAS A8 0 00 0
// 78 n_CS2 P9 1 10 1
// 79 LAN_RES T9 1 00 1
#define GAFR2_L_VAL 0x20000000
// 80 n_CS4 R13 0 00 0
#define GPDR2_VAL 0x0000c000
#define GAFR2_U_VAL 0x00000000
#define GPSR2_VAL 0x0000c000
#define GPSR0_OFFS (PXA2X0_GPSR0-PXA2X0_GPIO_BASE)
#define GPCR0_OFFS (PXA2X0_GPCR0-PXA2X0_GPIO_BASE)
#define GPSR1_OFFS (PXA2X0_GPSR1-PXA2X0_GPIO_BASE)
#define GPCR1_OFFS (PXA2X0_GPCR1-PXA2X0_GPIO_BASE)
#define GPSR2_OFFS (PXA2X0_GPSR2-PXA2X0_GPIO_BASE)
#define GPCR2_OFFS (PXA2X0_GPCR2-PXA2X0_GPIO_BASE)
#define GPDR0_OFFS (PXA2X0_GPDR0-PXA2X0_GPIO_BASE)
#define GPDR1_OFFS (PXA2X0_GPDR1-PXA2X0_GPIO_BASE)
#define GPDR2_OFFS (PXA2X0_GPDR2-PXA2X0_GPIO_BASE)
#define GAFR0_L_OFFS (PXA2X0_GAFR0_L-PXA2X0_GPIO_BASE)
#define GAFR0_U_OFFS (PXA2X0_GAFR0_U-PXA2X0_GPIO_BASE)
#define GAFR1_L_OFFS (PXA2X0_GAFR1_L-PXA2X0_GPIO_BASE)
#define GAFR1_U_OFFS (PXA2X0_GAFR1_U-PXA2X0_GPIO_BASE)
#define GAFR2_L_OFFS (PXA2X0_GAFR2_L-PXA2X0_GPIO_BASE)
#define GAFR2_U_OFFS (PXA2X0_GAFR2_U-PXA2X0_GPIO_BASE)
#define PSSR_OFFS (PXA2X0_PSSR-PXA2X0_PM_BASE)
.macro init_mpc_gpio
ldr r1, =PXA2X0_GPIO_BASE
ldr r0, =GPSR0_VAL // set GPIO outputs to default
str r0, [r1, #GPSR0_OFFS]
mvn r0, r0
str r0, [r1, #GPCR0_OFFS]
ldr r0, =GPSR1_VAL // set GPIO outputs to default
str r0, [r1, #GPSR1_OFFS]
mvn r0, r0
str r0, [r1, #GPCR1_OFFS]
ldr r0, =GPSR2_VAL // set GPIO outputs to default
str r0, [r1, #GPSR2_OFFS]
mvn r0, r0
str r0, [r1, #GPCR2_OFFS]
ldr r0, =GPDR0_VAL // GPIO direction
str r0, [r1, #GPDR0_OFFS]
ldr r0, =GPDR1_VAL // GPIO direction
str r0, [r1, #GPDR1_OFFS]
ldr r0, =GPDR2_VAL // GPIO direction
str r0, [r1, #GPDR2_OFFS]
ldr r0, =GAFR0_L_VAL // GPIO alternate function
str r0, [r1, #GAFR0_L_OFFS]
ldr r0, =GAFR0_U_VAL // GPIO alternate function
str r0, [r1, #GAFR0_U_OFFS]
ldr r0, =GAFR1_L_VAL // GPIO alternate function
str r0, [r1, #GAFR1_L_OFFS]
ldr r0, =GAFR1_U_VAL // GPIO alternate function
str r0, [r1, #GAFR1_U_OFFS]
ldr r0, =GAFR2_L_VAL // GPIO alternate function
str r0, [r1, #GAFR2_L_OFFS]
ldr r0, =GAFR2_U_VAL // GPIO alternate function
str r0, [r1, #GAFR2_U_OFFS]
ldr r1, =PXA2X0_PM_BASE
ldr r0, =0x20
str r0, [r1, #PSSR_OFFS] // enable GPIO inputs
.endm
/**********************************************************************************************************************
* LED
**********************************************************************************************************************/
// -7-
// | |
// 1 6
// | |
// -2-
// | |
// 3 5
// | |
// -4- 0
#define CYGHWR_LED_MACRO \
b 2f ;\
1: ;\
.byte 0xfb, 0x61, 0xdd, 0xf5 ;\
.byte 0x67, 0xb7, 0xbf, 0xe1 ;\
.byte 0xff, 0xf7, 0xef, 0x3f ;\
.byte 0x1d, 0x7d, 0x9f, 0x8f ;\
2: ;\
ldr r1, =PXA2X0_GPIO_BASE ;\
mov r0, #0x00ff0000 ;\
str r0, [r1, #GPSR1_OFFS] ;\
sub r0, pc, #((3f+4)-1b) ;\
3: ;\
ldrb r0, [r0, #\x] ;\
mov r0, r0, lsl #16 ;\
str r0, [r1, #GPCR1_OFFS] ;
/**********************************************************************************************************************
* initialize controller
**********************************************************************************************************************/
#if defined(CYG_HAL_STARTUP_ROM)
#define PLATFORM_SETUP1 _platform_setup1
#define CYGHWR_HAL_ARM_HAS_MMU
#else
#define PLATFORM_SETUP1
#endif
.macro _platform_setup1
.rept 0x20/4
nop
.endr
b 1f
.globl mpc50_static_info // Space for some static information
mpc50_static_info:
.byte 'M','P','C','5' // Magic
.rept 16
.long 0
.endr
1:
init_mmu_off // MMU on (and Cache)
init_mpc_gpio // GPIOs
LED(12)
init_sdram_cnt // SDRAM
LED(11)
init_intc_cnt // Interrupt Controller
LED(10)
init_clks // Clocks
LED(9)
init_mmu_cache_on // MMU and Cache
LED(8)
.endm
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -