📄 hal_platform_setup.h
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/*=============================================================================
//
// hal_platform_setup.h
//
// Platform specific support for HAL (assembly code)
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): <knud.woehler@microplex.de>
// Date: 2003-01-09
//
//####DESCRIPTIONEND####
//
//===========================================================================*/
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
#define CYGONCE_HAL_PLATFORM_SETUP_H
#include <pkgconf/system.h> // System-wide configuration info
#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
#include <cyg/hal/hal_pxa2x0.h> // Platform specific hardware definitions
#include <cyg/hal/hal_mmu.h> // MMU definitions
#include <cyg/hal/hal_mm.h> // more MMU definitions
#include <cyg/hal/mpc50.h>
/**********************************************************************************************************************
* MMU/Cache
**********************************************************************************************************************/
.macro init_mmu_cache_on
ldr r0, =0x2001
mcr p15, 0, r0, c15, c1, 0
mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
CPWAIT r0
mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
CPWAIT r0
mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
CPWAIT r0
// Icache on
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #MMU_Control_I
orr r0, r0, #MMU_Control_BTB // Enable the BTB
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
// create stack for "C"
ldr r1,=__startup_stack
ldr r2,=PXA2X0_RAM_BANK0_BASE
orr sp,r1,r2
bl hal_mmu_init // create MMU Tables
// Enable permission checks in all domains
ldr r0, =0x55555555
mcr p15, 0, r0, c3, c0, 0
// MMU on
ldr r2,=1f
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #MMU_Control_M
orr r0, r0, #MMU_Control_R
mcr p15, 0, r0, c1, c0, 0
mov pc,r2
nop
nop
nop
1:
mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
CPWAIT r0
// Dcache on
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #MMU_Control_C
mcr p15, 0, r0, c1, c0, 0
CPWAIT r0
// clean/drain/flush the main Dcache
mov r1, #0xc0000000
mov r0, #1024
2:
mcr p15, 0, r1, c7, c2, 5
add r1, r1, #32
subs r0, r0, #1
bne 2b
// clean/drain/flush the mini Dcache
//ldr r1, =(DCACHE_FLUSH_AREA+DCACHE_SIZE) // use a CACHEABLE area of
mov r0, #64 // number of lines in the mini Dcache
3:
mcr p15, 0, r1, c7, c2, 5 // allocate a Dcache line
add r1, r1, #32 // increment the address to
subs r0, r0, #1 // decrement the loop count
bne 3b
// flush Dcache
mcr p15, 0, r0, c7, c6, 0
CPWAIT r0
// drain the write & fill buffers
mcr p15, 0, r0, c7, c10, 4
CPWAIT r0
.endm
.macro init_mmu_off
mov r0, #0x78
mcr p15, 0, r0, c1, c0, 0 // caches off -- MMU off or ID map
mcr p15, 0, r0, c7, c7, 0 // Invalidate the I & D cache, mini- d cache, and BTB
mcr p15, 0, r0, c7, c10, 4 // Drain write buffer -- r0 ignored
CPWAIT r0
nop
nop
nop
nop
mvn r0, #0
mcr p15, 0, r0, c3, c0, 0
.endm
/**********************************************************************************************************************
* Clock
**********************************************************************************************************************/
#define CCCR_OFFS (PXA2X0_CCCR-PXA2X0_CLK_BASE)
.macro init_clks
ldr r1, =PXA2X0_CLK_BASE
// TurboMode=400MHz/RunMode=200MHz/Memory=100MHz/SDRam=100MHz
// ldr r0, =(PXA2X0_CCCR_L27 | PXA2X0_CCCR_M2 | PXA2X0_CCCR_N20)
// TurboMode=300MHz/RunMode=200MHz/Memory=100MHz/SDRam=100MHz
// ldr r0, =(PXA2X0_CCCR_L27 | PXA2X0_CCCR_M2 | PXA2X0_CCCR_N15)
adr r0, mpc50_static_info
ldr r0, [r0, #MPC50_VAL_OFFS_CCCR]
str r0, [r1, #CCCR_OFFS] // set Core Clock
mov r0, #3
mcr p14, 0, r0, c6, c0, 0 // Turbo Mode on
.endm
/**********************************************************************************************************************
* Interrupt controller
**********************************************************************************************************************/
#define ICLR_OFFS (PXA2X0_ICLR-PXA2X0_IC_BASE)
#define ICMR_OFFS (PXA2X0_ICMR-PXA2X0_IC_BASE)
.macro init_intc_cnt
ldr r1, =PXA2X0_IC_BASE
mov r0, #0
str r0, [r1, #ICLR_OFFS] // clear Interrupt level Register
str r0, [r1, #ICMR_OFFS] // clear Interrupt mask Register
.endm
/**********************************************************************************************************************
* SDRAM
**********************************************************************************************************************/
//#define MDCNFG_VAL 0x094B094B // SDRAM Config Reg (32Bit, 9 Col, 13 Row, 2 Bank, CL2)
//#define MDREFR_VAL 0x0005b018 // SDRAM Refresh Reg SDCLK=memory clock
//#define MDREFR_VAL 0x000ff018 // SDRAM Refresh Reg SDCLK=1/2 memory clock
#define MDMRS_VAL 0x00000000 // SDRAM Mode Reg Set Config Reg
#define MSC0_VAL 0x199123da // CS1(FPGA)/CS0(Flash)
#define MSC1_VAL 0x7ff07ff1 // CS3(not used)/CS2(ETH)
#define OSCR_OFFS (PXA2X0_OSCR-PXA2X0_OSTIMER_BASE)
#define MDREFR_OFFS (PXA2X0_MDREFR-PXA2X0_MEMORY_CTL_BASE)
#define MDCNFG_OFFS (PXA2X0_MDCNFG-PXA2X0_MEMORY_CTL_BASE)
#define MDMRS_OFFS (PXA2X0_MDMRS-PXA2X0_MEMORY_CTL_BASE)
#define MSC0_OFFS (PXA2X0_MSC0-PXA2X0_MEMORY_CTL_BASE)
#define MSC1_OFFS (PXA2X0_MSC1-PXA2X0_MEMORY_CTL_BASE)
#define MSC2_OFFS (PXA2X0_MSC2-PXA2X0_MEMORY_CTL_BASE)
.macro init_sdram_cnt
// Hardware Reset Operation (S. 5-83)
// Step 1
// wait 200 usec
ldr r1, =PXA2X0_OSTIMER_BASE // set OS Timer Count
mov r0, #0
str r0, [r1, #OSCR_OFFS]
ldr r2, =0x300 // wait 200 usec
61:
ldr r0, [r1, #OSCR_OFFS]
cmp r2, r0
bgt 61b
ldr r1, =PXA2X0_MEMORY_CTL_BASE
ldr r0, =MSC0_VAL
str r0, [r1, #MSC0_OFFS] // FPGA/Flash
ldr r0, =MSC1_VAL
str r0, [r1, #MSC1_OFFS] // ETH
// Refresh Register
//ldr r3, =MDREFR_VAL // load SDRAM refresh info
adr r3, mpc50_static_info
ldr r3, [r3, #MPC50_VAL_OFFS_MDREFR]
ldr r2, =0xFFF // DRI field
and r3, r3, r2
ldr r4, [r1, #MDREFR_OFFS] // read Reset Status
bic r4, r4, r2
bic r4, r4, #(0x01000000 | 0x02000000) // clear K1Free, K2Free,
bic r4, r4, #0x00004000 // K0DB2
orr r4, r4, r3 // add DRI field
str r4, [r1, #MDREFR_OFFS] //
ldr r4, [r1, #MDREFR_OFFS]
// Step 2
//
// Step 3
//ldr r3, =MDREFR_VAL // load SDRAM Refresh Info
adr r3, mpc50_static_info
ldr r3, [r3, #MPC50_VAL_OFFS_MDREFR]
ldr r2, =0x000f0000
and r3, r3, r2
orr r4, r4, r3
str r4, [r1, #MDREFR_OFFS]
ldr r4, [r1, #MDREFR_OFFS]
bic r4, r4, #0x00400000 // Self Refresh off
str r4, [r1, #MDREFR_OFFS]
ldr r4, [r1, #MDREFR_OFFS]
orr r4, r4, #0x00008000 // SDCKE1 on
str r4, [r1, #MDREFR_OFFS]
ldr r4, [r1, #MDREFR_OFFS]
orr r4, r4, #0x00800000 // K0Free on
str r4, [r1, #MDREFR_OFFS]
ldr r4, [r1, #MDREFR_OFFS]
nop
nop
// Step 4
//ldr r2, =MDCNFG_VAL
adr r2, mpc50_static_info
ldr r2, [r2, #MPC50_VAL_OFFS_MDCNFG]
bic r2, r2, #0x0003 // DE1-0
bic r2, r2, #0x00030000 // DE3-2
str r2, [r1, #MDCNFG_OFFS]
// Step 5
// wait 200 usec
ldr r1, =PXA2X0_OSTIMER_BASE
mov r0, #0
str r0, [r1, #OSCR_OFFS]
ldr r2, =0x300
71:
ldr r0, [r1, #OSCR_OFFS]
cmp r2, r0
bgt 71b
// Step 6
mov r0, #0x78
mcr p15, 0, r0, c1, c0, 0 // (caches off, MMU off, etc.)
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