hal_platform_setup.h

开放源码实时操作系统源码.

	beq	i2c_error		// Kick out of SDRAM initialization if timeout occurs
	ldr	r0, [r11, #I2C_ISR0]	// Load I2C Status Reg into R0
	ands	r3, r0, #ISR_EMPTY	// Bit #6 is checked, IDBR Transmit Empty
	beq	0b			// If bit = 0 then branch to 0 and check again
	str	r0, [r11, #I2C_ISR0]	// Write back status to clear
1:
	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_3
	// ====================================================================
		
	// *** Read SDRAM PD data ***

	// *** Put out address, with READ mode ***

	//  Set SDRAM module address and read mode
	mov	r0, #SDRAM_DEVID	// Load slave address for SDRAM module (0xA2)
	orr	r1, r0, #IDBR_MODE	// Set read bit (bit #0)
	str	r1, [r11, #I2C_IDBR0]	// Store to data register

	//  Send next read request
	ldr	r1, [r11, #I2C_ICR0]	// read the current Control Register value
	bic	r1, r1,	#ICR_STOP	// No stop bit
	orr	r1, r1,	#ICR_START | ICR_TRANSFER
	str	r1, [r11, #I2C_ICR0]	// Store to control register

	// Wait for transmit empty status
	mov	r1, #I2C_TIMOUT		// Initialize I2C timeout counter
    0:	subs	r1, r1, #1		// Increment I2C timeout counter (r1 = r1 + 1)
	beq	i2c_error		// Kick out of SDRAM initialization if timeout occurs
	ldr	r0, [r11, #I2C_ISR0]	// Load I2C Status Reg into R0
	ands	r3, r0, #ISR_EMPTY	// Bit #6 is checked, IDBR Transmit Empty
	beq	0b			// If bit = 0 then branch to 0 and check again
	str	r0, [r11, #I2C_ISR0]	// Write back status to clear

	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_9, DISPLAY_4
	// ====================================================================

  spd_loop:
	// read the next Byte of Serial Presence Detect data

	ldr	r1, [r11, #I2C_ICR0]	// read the current Control Register value
	bic	r1, r1,	#ICR_START	// No start bit (already started)
	orr	r1, r1, #ICR_TRANSFER	// Set transfer bit - bit is self_clearing

	// we have to set NACK before reading the last byte
	add     r2, r6, #1
	cmp	r2, r7			// r7 = 64 (decimal) so if r6 = 64, this is the last byte to be read
	orreq	r1, r1, #ICR_ACK | ICR_STOP
	str	r1, [r11, #I2C_ICR0]	// Store to control register

	// Wait for read full status
	mov	r1, #I2C_TIMOUT		// Initialize I2C timeout counter
    0:	subs	r1, r1, #1		// decrement timeout
	beq	i2c_error		// Kick out of SDRAM initialization if timeout occurs
	ldr	r0, [r11, #I2C_ISR0]	// Load I2C Status Reg into R0
	ands	r3, r0, #ISR_FULL	// Bit #7 is checked
	beq	0b			// If bit = 0 then branch to 0 and check again
	str	r0, [r11, #I2C_ISR0]	// Write back status to clear

	ldr	r1, [r11, #I2C_IDBR0]	// Read the byte

	// check for checksum byte
	subs	r2, r6, #SPD_CHECKSUM
	addne	r5, r5, r1		// Add it to the checksum if not the checksum byte
	bne	1f			// skip checksum comparison
	and	r5, r5, #0xff		//	against the calculated checksum
	cmp	r1, r5
	beq	spd_continue

	// bad checksum
	HEX_DISPLAY r2, r3, DISPLAY_7, DISPLAY_7
	0: b 0b

    1:
	// Check for bank count byte
	subs	r2, r6, #SPD_BANKCNT
	moveq	r8, r1			// Store bank count
	beq	spd_continue
	
	// Check for ECC
	subs	r2, r6, #SPD_CONFIG
	bne	1f
	subs	r2, r1, #2
	addeq	r14, r14, #1
	b	spd_continue
    1:

	// Check for refresh rate
	subs	r2, r6, #SPD_REFRESH
	bne	1f

	ands	r2, r1, #0x7f
	moveq	r9, #RFR_15_6us
	subs	r3, r2, #1
	moveq	r9, #RFR_3_9us
	subs	r3, r2, #2
	moveq	r9, #RFR_7_8us

	b	spd_continue

    1:
 	// Check for SDRAM width byte
	subs	r2, r6, #SPD_SDRAM_WIDTH
	bne	1f

	ands	r2, r1, #0x10		// Check for data width of 16
	orr	r8, r8, r2, lsl #3      // set b7 in r8 if x16

#if 0 // drive strength doesn't depend on width
	ldreq   r2, =x8_table		// x8 if bit not set
	ldrne   r2, =x16_table		// x16 if bit not set
	b	init_drive_strength

    x16_table:
	.word   0x18	// Data Bus Pull Up
	.word   0x18	// Data Bus Pull Down
	.word   0x22	// Clock Pull Up
	.word   0x20	// Clock Pull Down
	.word   0x30	// Clock Enable Pull Up
	.word   0x30	// Clock Enable Pull Down
	.word   0x30	// Chip Select Pull Up
	.word   0x30	// Chip Select Pull Down
	.word   0x18	// Receive Enable Pull Up
	.word   0x18	// Receive Enable Pull Down
	.word   0x3c	// Address Bus Pull Up
	.word   0x3c	// Address Bus Pull Down

    x8_table:
	.word   0x18	// Data Bus Pull Up
	.word   0x18	// Data Bus Pull Down
	.word   0x22	// Clock Pull Up
	.word   0x20	// Clock Pull Down
	.word   0x30	// Clock Enable Pull Up
	.word   0x30	// Clock Enable Pull Down
	.word   0x30	// Chip Select Pull Up
	.word   0x30	// Chip Select Pull Down
	.word   0x18	// Receive Enable Pull Up
	.word   0x18	// Receive Enable Pull Down
	.word   0x3c	// Address Bus Pull Up
	.word   0x3c	// Address Bus Pull Down
#else
	b	spd_continue

    registered_table:
	.word   13	// Data Bus Pull Up
	.word   13	// Data Bus Pull Down
	.word   34	// Clock Pull Up
	.word   32	// Clock Pull Down
	.word   48	// Clock Enable Pull Up
	.word   48	// Clock Enable Pull Down
	.word   13	// Chip Select Pull Up
	.word   13	// Chip Select Pull Down
	.word   13	// Receive Enable Pull Up
	.word   13	// Receive Enable Pull Down
	.word   13	// Address Bus Pull Up
	.word   13	// Address Bus Pull Down

    unbuffered_table:
	.word   13	// Data Bus Pull Up
	.word   13	// Data Bus Pull Down
	.word   34	// Clock Pull Up
	.word   32	// Clock Pull Down
	.word   48	// Clock Enable Pull Up
	.word   48	// Clock Enable Pull Down
	.word   24	// Chip Select Pull Up
	.word   24	// Chip Select Pull Down
	.word   13	// Receive Enable Pull Up
	.word   13	// Receive Enable Pull Down
	.word   24	// Address Bus Pull Up
	.word   24	// Address Bus Pull Down
#endif

    init_drive_strength:

        ldr	r1, =MCU_DBUDSR
	mov	r3, #12         // 12 contiguous registers to set
    0:
	ldr	r0, [r2], #4	// load value
        str	r0, [r1], #4	// store to register
	subs	r3, r3, #1
	bne	0b
	b	spd_continue
    1:

	// Check for module attribute byte
	subs	r2, r6, #SPD_MOD_ATTRIB
	bne	1f
        ldr     r0, =MCU_SDCR
	mov     r2, #SDCR_INIT_VAL
	ands	r3, r1, #SPD_ATTRIB_REG_CTL  // check for registered modules
        beq     2f      
	orr	r2, r2, #2
	str	r2, [r0]
	ldr     r2, =registered_table
	b	init_drive_strength
    2:
	str	r2, [r0]
	ldr     r2, =unbuffered_table
	b	init_drive_strength
    1:

	// Check for bank size byte
	subs	r2, r6, #SPD_BANKSZ
	bne	1f
	mov	r10, r1, lsl #2		// Store bank size in Mbytes (shift left 2 bits)
	and     r3, r8, #0x7f           // isolate bank count     
	mul	r2, r3, r10		// Multiply by bank count to get DRAM size in MB
	mov	r4, r2, lsl #20		// Convert size to bytes  - r4 contains DRAM size in bytes
	b	spd_continue
    1:

  spd_continue:
	// Continue reading bytes if not done
	add	r6, r6, #1	// Increment byte counter
	cmp	r6, r7
	bne	spd_loop
	
	b	i2c_disable

	.ltorg
    i2c_error:
	// hit the leds if an error occurred
	HEX_DISPLAY r2, r3, DISPLAY_5, DISPLAY_5
	b i2c_error
    i2c_disable:
	//  Disable I2C Interface Unit
	ldr	r1, [r11, #I2C_ICR0] 
	bic	r1, r1, #ICR_ENB | ICR_SCLENB	// Disable I2C unit
	str	r1, [r11, #I2C_ICR0]
	
	// At this point, r4 = SDRAM size in bytes, r8 = Bank count, r10 = bank size in MB


	// *** SDRAM setup ***

	// Set the DDR SDRAM Base Register - SDBR (the lowest address for memory)
        ldr     r0, =MCU_SDBR
        mov     r1, #SDRAM_PHYS_BASE
        str     r1, [r0]

	// Set up bank 0 register
	subs	r1, r10, #32
	moveq	r0, #SBR_32MEG		// Program SDRAM Bank0 Boundary register to 32 MB
	beq	1f
	subs	r1, r10, #64		// do we have 64 MB banks?
	moveq	r0, #SBR_64MEG		// Program SDRAM Bank0 Boundary register to 64 MB
	beq	1f
	subs	r1, r10, #128		// do we have 128 MB banks?
	moveq	r0, #SBR_128MEG		// Program SDRAM Bank0 Boundary register to 128 MB
	beq	1f
	subs	r1, r10, #256		// do we have 256 MB banks?
	moveq	r0, #SBR_256MEG		// Program SDRAM Bank0 Boundary register to 64 MB
	beq	1f
	subs	r1, r10, #512		// do we have 512 MB banks?
	moveq	r0, #SBR_512MEG		// Program SDRAM Bank0 Boundary register to 64 MB
	beq	1f
	
     bank_err:
  	HEX_DISPLAY r2, r3, DISPLAY_F, DISPLAY_F
	b	bank_err
    1:
        mov     r1, #SDRAM_PHYS_BASE
        mov     r2, #0x1f
        and     r2, r2, r1, lsr #25
	add	r2, r2, r0

	ands	r1, r8, #0x80
	and	r8, r8, #0x7f
	beq	1f
	// x16
	subs	r1, r10, #128
	addeq   r2, r2, #0x80000000
    1:
	ldr	r1, =MCU_SBR0
	str	r2, [r1]		// store SBR0

	subs	r1, r8, #2		// do we have 2 banks???
	addeq	r2, r2, r0              // SBR1 == SBR0+r0 if two banks
	ldr	r1, =MCU_SBR1
	str	r2, [r1]

 	// ====================================================================
	HEX_DISPLAY r0, r1, DISPLAY_A, DISPLAY_5
	// ====================================================================
		
	DELAY_FOR 0x1800000, r0

	//  Disable the refresh counter by setting the RFR to zero.
        // (from section 7.2.2.6 of the Verde technical specification)
        ldr     r0, =MCU_RFR
        mov     r1, #0
        str     r1, [r0]

        // Issue one NOP cycle after the 200 us device deselect. A NOP is 
        // accomplished by setting the SDIR to 0101.
        ldr     r0, =MCU_SDIR
        mov     r1, #SDIR_CMD_NOP
        str     r1, [r0]
	
        // Issue a precharge-all command to the DDR SDRAM interface by setting 
        // the SDIR to 0100.
        mov     r1, #SDIR_CMD_PRECHARGE_ALL
        str     r1, [r0]

        // Issue an extended-mode-register-set command to enable the DLL by 
        // writing 0110 to the SDIR.
        NOPs    8
		
        mov     r1, #SDIR_CMD_ENABLE_DLL
        str     r1, [r0]

        // After waiting T mrd cycles (4 clocks at 200 MHz), issue a 
        // mode-register-set command by writing to the SDIR to program the DDR 
        // SDRAM parameters and to Reset the DLL. Setting the SDIR to 0010 
        // programs the MCU for CAS Latency of two while setting the SDIR to 0011
        // programs the MCU for CAS Latency of two and one-half. The MCU supports