📄 mb93091_misc.c
字号:
case 0x11:/* FR501 */
model = "501";
break;
case 0x31:/* FR555 */
model = "555";
cb_nr = 41;
break;
default:
model = NULL;
diag_sprintf(HAL_PLATFORM_EXTRA, "(PSR %02x)", psr >> 24);
break;
}
if (model) {
diag_sprintf(HAL_PLATFORM_CPU, "Fujitsu FR%s", model);
diag_sprintf(HAL_PLATFORM_BOARD, "MB93%s evaluation board", model);
}
if (cb_nr) {
diag_sprintf(HAL_PLATFORM_EXTRA, "(CB%d)", cb_nr);
}
if (cb_nr == 70 || cb_nr == 451) {
HAL_READ_UINT16(_MB93091_FPGA_CLKRS, tmp);
if (tmp & 0x1000)
_system_clock = 60000000;
else
_system_clock = ((tmp & 0xf00) * 100 / 0x100 +
(tmp & 0xf0) * 10 / 0x10 +
(tmp & 0xf)) * 100000;
/* Check for motherboard. */
HAL_READ_UINT16(_MB93091_FPGA_GPHL, tmp);
if (tmp & 0x100)
_mb93091_has_vdk = 0;
/* Turn on CS6# for onboard DM9000 NIC */
HAL_READ_UINT32(_FRV400_LBUS_GCR, u32);
u32 |= (1 << 6);
HAL_WRITE_UINT32(_FRV400_LBUS_GCR, u32);
}
// Set up system clock if it wasn't already detected
// This will break if a board is standalone but hasn't had its
// _system_clock set by the above.
if (!_system_clock && _mb93091_has_vdk) {
// First, read the motherboard clock switches to see the frequency
// it's generating. AV9110_CLKOUT/MHz = 12.5 * <N> / 24.
HAL_READ_UINT32(_MB93091_MB_CLKSW, clk);
_system_clock = (((clk&0xFF) * 125U * 100000U) / 24U);
// The FR401 doubles the clock signal. The FR555 _can_ do, according to
// the setting of the 2XCLK jumper. Since we can't actually _read_ the
// current setting of 2XCLK, assume it's still set to the default, which
// is to double the clock also.
if ((psr & 0xff000000) == 0x20000000 ||
(psr & 0xff000000) == 0x31000000)
_system_clock <<= 1;
}
if (!_system_clock)
_system_clock = 60000000; /* Guess */
// If the chip is configured to halve CLKIN, adjust for that.
HAL_READ_UINT32(_FRVGEN_CLK_CTRL, clkc);
if (clkc & _FRVGEN_CLK_CTRL_P0)
_system_clock >>= 1;
// Set scalers to achieve 1us resolution in timer
HAL_WRITE_UINT8(_FRVGEN_TPRV, _system_clock / (1000*1000));
HAL_WRITE_UINT8(_FRVGEN_TCKSL0, 0x80);
HAL_WRITE_UINT8(_FRVGEN_TCKSL1, 0x80);
HAL_WRITE_UINT8(_FRVGEN_TCKSL2, 0x80);
// Set LCD welcome string.
if (_mb93091_has_vdk)
setlcd(model);
// Make sure UART clock prescaler is at power-on reset setting.
HAL_WRITE_UINT32(_FRVGEN_UCPSR, 0);
HAL_WRITE_UINT32(_FRVGEN_UCPVR, 0);
hal_if_init();
// Initialize real-time clock (for delays, etc, even if kernel doesn't use it)
hal_clock_initialize(CYGNUM_HAL_RTC_PERIOD);
#ifdef CYGPKG_IO_PCI
if (_mb93091_has_vdk)
_mb93091_pci_init();
#endif
}
// Is DM9000 present?
int cyg_hal_dm9000_present(void) {
return (!strcmp(HAL_PLATFORM_EXTRA, "(CB70)") ||
!strcmp(HAL_PLATFORM_CPU, "Fujitsu FR451"));
}
//
// Interrupt control
//
void hal_interrupt_mask(int vector)
{
cyg_uint16 _mask;
switch (vector) {
case CYGNUM_HAL_INTERRUPT_LAN:
HAL_READ_UINT16(_MB93091_FPGA_IRQ_MASK, _mask);
_mask |= _MB93091_FPGA_IRQ_LAN;
HAL_WRITE_UINT16(_MB93091_FPGA_IRQ_MASK, _mask);
break;
}
HAL_READ_UINT16(_FRVGEN_IRC_MASK, _mask);
_mask |= (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
HAL_WRITE_UINT16(_FRVGEN_IRC_MASK, _mask);
}
void hal_interrupt_unmask(int vector)
{
cyg_uint16 _mask;
switch (vector) {
case CYGNUM_HAL_INTERRUPT_LAN:
HAL_READ_UINT16(_MB93091_FPGA_IRQ_MASK, _mask);
_mask &= ~_MB93091_FPGA_IRQ_LAN;
HAL_WRITE_UINT16(_MB93091_FPGA_IRQ_MASK, _mask);
break;
}
HAL_READ_UINT16(_FRVGEN_IRC_MASK, _mask);
_mask &= ~(1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
HAL_WRITE_UINT16(_FRVGEN_IRC_MASK, _mask);
}
void hal_interrupt_acknowledge(int vector)
{
cyg_uint16 _mask;
switch (vector) {
case CYGNUM_HAL_INTERRUPT_LAN:
HAL_WRITE_UINT16(_MB93091_FPGA_IRQ_REQUEST, // Clear LAN interrupt
0x7FFE & ~_MB93091_FPGA_IRQ_LAN);
break;
}
_mask = (1<<(vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1));
HAL_WRITE_UINT16(_FRVGEN_IRC_RC, _mask);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRL, 0x10); // Clears IRL latch
}
//
// Configure an interrupt
// level - boolean (0=> edge, 1=>level)
// up - edge: (0=>falling edge, 1=>rising edge)
// level: (0=>low, 1=>high)
//
void hal_interrupt_configure(int vector, int level, int up)
{
cyg_uint16 _irr, _tmr, _trig;
if (level) {
if (up) {
_trig = 0; // level, high
} else {
_trig = 1; // level, low
}
} else {
if (up) {
_trig = 2; // edge, rising
} else {
_trig = 3; // edge, falling
}
}
switch (vector) {
case CYGNUM_HAL_INTERRUPT_TIMER0:
HAL_READ_UINT16(_FRVGEN_IRC_IRR5, _irr);
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR5, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xFFFC) | (_trig<<0);
HAL_WRITE_UINT16(_FRVGEN_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_TIMER1:
HAL_READ_UINT16(_FRVGEN_IRC_IRR5, _irr);
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR5, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xFFF3) | (_trig<<2);
HAL_WRITE_UINT16(_FRVGEN_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_TIMER2:
HAL_READ_UINT16(_FRVGEN_IRC_IRR5, _irr);
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR5, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xFFCF) | (_trig<<4);
HAL_WRITE_UINT16(_FRVGEN_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_DMA0:
HAL_READ_UINT16(_FRVGEN_IRC_IRR4, _irr);
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR4, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xFCFF) | (_trig<<8);
HAL_WRITE_UINT16(_FRVGEN_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_DMA1:
HAL_READ_UINT16(_FRVGEN_IRC_IRR4, _irr);
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR4, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
HAL_WRITE_UINT16(_FRVGEN_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_DMA2:
HAL_READ_UINT16(_FRVGEN_IRC_IRR4, _irr);
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR4, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_ITM0, _tmr);
_tmr = (_tmr & 0xCFFF) | (_trig<<12);
HAL_WRITE_UINT16(_FRVGEN_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_DMA3:
HAL_READ_UINT16(_FRVGEN_IRC_IRR4, _irr);
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR4, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_ITM0, _tmr);
_tmr = (_tmr & 0x3FFF) | (_trig<<14);
HAL_WRITE_UINT16(_FRVGEN_IRC_ITM0, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_UART0:
HAL_READ_UINT16(_FRVGEN_IRC_IRR6, _irr);
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR6, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_ITM1, _tmr);
_tmr = (_tmr & 0xFCFF) | (_trig<<8);
HAL_WRITE_UINT16(_FRVGEN_IRC_ITM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_UART1:
HAL_READ_UINT16(_FRVGEN_IRC_IRR6, _irr);
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR6, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_ITM1, _tmr);
_tmr = (_tmr & 0xF3FF) | (_trig<<10);
HAL_WRITE_UINT16(_FRVGEN_IRC_ITM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_EXT0:
HAL_READ_UINT16(_FRVGEN_IRC_IRR3, _irr);
_irr = (_irr & 0xFFF0) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<0);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR3, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_TM1, _tmr);
_tmr = (_tmr & 0xFFFC) | (_trig<<0);
HAL_WRITE_UINT16(_FRVGEN_IRC_TM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_EXT1:
HAL_READ_UINT16(_FRVGEN_IRC_IRR3, _irr);
_irr = (_irr & 0xFF0F) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<4);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR3, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_TM1, _tmr);
_tmr = (_tmr & 0xFFF3) | (_trig<<2);
HAL_WRITE_UINT16(_FRVGEN_IRC_TM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_EXT2:
HAL_READ_UINT16(_FRVGEN_IRC_IRR3, _irr);
_irr = (_irr & 0xF0FF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<8);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR3, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_TM1, _tmr);
_tmr = (_tmr & 0xFFCF) | (_trig<<4);
HAL_WRITE_UINT16(_FRVGEN_IRC_TM1, _tmr);
break;
case CYGNUM_HAL_INTERRUPT_EXT3:
HAL_READ_UINT16(_FRVGEN_IRC_IRR3, _irr);
_irr = (_irr & 0x0FFF) | ((vector-CYGNUM_HAL_VECTOR_EXTERNAL_INTERRUPT_LEVEL_1+1)<<12);
HAL_WRITE_UINT16(_FRVGEN_IRC_IRR3, _irr);
HAL_READ_UINT16(_FRVGEN_IRC_TM1, _tmr);
_tmr = (_tmr & 0xFF3F) | (_trig<<6);
HAL_WRITE_UINT16(_FRVGEN_IRC_TM1, _tmr);
break;
default:
; // Nothing to do
};
}
void hal_interrupt_set_level(int vector, int level)
{
// UNIMPLEMENTED(__FUNCTION__);
}
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