frv400.h

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//==========================================================================
//
//      frv400.h
//
//      HAL misc board support definitions for Fujitsu MB93091 (FR-V 400)
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
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// the terms of the GNU General Public License as published by the Free
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
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// or inline functions from this file, or you compile this file and link it
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//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    gthomas
// Contributors: gthomas
// Date:         2001-09-07
// Purpose:      Platform register definitions
// Description:  
//
//####DESCRIPTIONEND####
//
//========================================================================*/

#ifndef __HAL_FRV400_H__
#define __HAL_FRV400_H__ 1

// Common

// Processor status register
#define _PSR_PIVL_SHIFT 3
#define _PSR_PIVL_MASK  (0xF<<(_PSR_PIVL_SHIFT))  // Interrupt mask level
#define _PSR_S          (1<<2)                    // Supervisor state
#define _PSR_PS         (1<<1)                    // Previous supervisor state
#define _PSR_ET         (1<<0)                    // Enable interrupts

// Hardware status register
#define _HSR0_ICE       (1<<31)                   // Instruction cache enable
#define _HSR0_DCE       (1<<30)                   // Data cache enable
#define _HSR0_IMMU      (1<<26)                   // Instruction MMU enable
#define _HSR0_DMMU      (1<<25)                   // Data MMU enable

// Debug Control Register
#define _DCR_EBE        (1 << 30) // Exception break enable bit 
#define _DCR_SE         (1 << 29) // Single-step break enable bit 
#define _DCR_IBM        (1 << 28) // Instruction Break Mask (disable bit)
#define _DCR_DRBE0      (1 << 19) // READ dbar0
#define _DCR_DWBE0      (1 << 18) // WRITE dbar0
#define _DCR_DDBE0      (1 << 17) // Data-match for access to dbar0
#define _DCR_DBASE0     (1 << 17) // offset
#define _DCR_DRBE1      (1 << 16)
#define _DCR_DWBE1      (1 << 15)
#define _DCR_DDBE1      (1 << 14)
#define _DCR_DBASE1     (1 << 14)
//#define _DCR_DRBE2      (1 << 13) // 2 and 3 not supported in real hardware
//#define _DCR_DWBE2      (1 << 12)
//#define _DCR_DDBE2      (1 << 11)
//#define _DCR_DRBE3      (1 << 10)
//#define _DCR_DWBE3      (1 << 9)
//#define _DCR_DDBE3      (1 << 8)
#define _DCR_IBE0       (1 << 7)
#define _DCR_IBCE0      (1 << 6)
#define _DCR_IBE1       (1 << 5)
#define _DCR_IBCE1      (1 << 4)
#define _DCR_IBE2       (1 << 3)
#define _DCR_IBCE2      (1 << 2)
#define _DCR_IBE3       (1 << 1)
#define _DCR_IBCE3      (1 << 0)

// Break PSR Save Register
#define _BPSR_BS	(1 << 12)
#define _BPSR_BET	(1 << 0)

// Break Request Register
#define _BRR_EB         (1 << 30)
#define _BRR_CB         (1 << 29)
#define _BRR_TB         (1 << 28)
#define _BRR_DB0        (1 << 11)
#define _BRR_DB1        (1 << 10)
#define _BRR_IB0        (1 << 7)
#define _BRR_IB1        (1 << 6)
#define _BRR_IB2        (1 << 5)
#define _BRR_IB3        (1 << 4)
#define _BRR_CBB        (1 << 3)
#define _BRR_BB         (1 << 2)
#define _BRR_SB         (1 << 1)
#define _BRR_ST         (1 << 0)


// Platform specifics

// SDRAM Controller
#define _FRV400_SDRAM_CP  0xFE000400              // Controller protect
#define _FRV400_SDRAM_CFG 0xFE000410              // Configuration
#define _FRV400_SDRAM_CTL 0xFE000418              // Control
#define _FRV400_SDRAM_MS  0xFE000420              // Mode select
#define _FRV400_SDRAM_STS 0xFE000428              // Status
#define _FRV400_SDRAM_RCN 0xFE000430              // Refresh control
#define _FRV400_SDRAM_ART 0xFE000438              // Auto-refresh timer
#define _FRV400_SDRAM_AN0 0xFE000500              // Address #0
#define _FRV400_SDRAM_AN1 0xFE000508              // Address #1
#define _FRV400_SDRAM_BR0 0xFE000E00              // Base register #0
#define _FRV400_SDRAM_BR1 0xFE000E08              // Base register #1
#define _FRV400_SDRAM_AM0 0xFE000F00              // Address mask #0
#define _FRV400_SDRAM_AM1 0xFE000F08              // Address mask #1

// Local bus control
#define _FRV400_LBUS_CP   0xFE000000              // Controller protect
#define _FRV400_LBUS_EST  0xFE000020              // Error status
#define _FRV400_LBUS_EAD  0xFE000028              // Error address
#define _FRV400_LBUS_CR0  0xFE000100              // Configuration - space #0
#define _FRV400_LBUS_CR1  0xFE000108              // Configuration - space #1
#define _FRV400_LBUS_CR2  0xFE000110              // Configuration - space #2
#define _FRV400_LBUS_CR3  0xFE000118              // Configuration - space #3
#define _FRV400_LBUS_BR0  0xFE000C00              // Slave - base address #0
#define _FRV400_LBUS_BR1  0xFE000C08              // Slave - base address #1
#define _FRV400_LBUS_BR2  0xFE000C10              // Slave - base address #2
#define _FRV400_LBUS_BR3  0xFE000C18              // Slave - base address #3
#define _FRV400_LBUS_AM0  0xFE000D00              // Slave - address mask #0
#define _FRV400_LBUS_AM1  0xFE000D08              // Slave - address mask #1
#define _FRV400_LBUS_AM2  0xFE000D10              // Slave - address mask #2
#define _FRV400_LBUS_AM3  0xFE000D18              // Slave - address mask #3

// PCI Bridge (on motherboard)
#define _FRV400_PCI_SLBUS_CONFIG       0x10000000
#define _FRV400_PCI_ECS0_CONFIG        0x10000008