📄 var_intr.h
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#define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX 88
#define CYGNUM_HAL_INTERRUPT_RESERVED_89 89
#define CYGNUM_HAL_INTERRUPT_RESERVED_90 90
#define CYGNUM_HAL_INTERRUPT_RESERVED_91 91
#define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX 92
#define CYGNUM_HAL_INTERRUPT_RESERVED_93 93
#define CYGNUM_HAL_INTERRUPT_RESERVED_94 94
#define CYGNUM_HAL_INTERRUPT_RESERVED_95 95
#define CYGNUM_HAL_INTERRUPT_SERIAL_2_RX 96
#define CYGNUM_HAL_INTERRUPT_RESERVED_97 97
#define CYGNUM_HAL_INTERRUPT_RESERVED_98 98
#define CYGNUM_HAL_INTERRUPT_RESERVED_99 99
#define CYGNUM_HAL_INTERRUPT_SERIAL_2_TX 100
#define CYGNUM_HAL_INTERRUPT_RESERVED_101 101
#define CYGNUM_HAL_INTERRUPT_RESERVED_102 102
#define CYGNUM_HAL_INTERRUPT_RESERVED_103 103
#define CYGNUM_HAL_INTERRUPT_RESERVED_104 104
#define CYGNUM_HAL_INTERRUPT_RESERVED_105 105
#define CYGNUM_HAL_INTERRUPT_RESERVED_106 106
#define CYGNUM_HAL_INTERRUPT_RESERVED_107 107
#define CYGNUM_HAL_INTERRUPT_TD 108
#define CYGNUM_HAL_INTERRUPT_RESERVED_109 109
#define CYGNUM_HAL_INTERRUPT_RESERVED_110 110
#define CYGNUM_HAL_INTERRUPT_RESERVED_111 111
#define CYGNUM_HAL_INTERRUPT_AV 112
#define CYGNUM_HAL_INTERRUPT_RESERVED_113 113
#define CYGNUM_HAL_INTERRUPT_RESERVED_114 114
#define CYGNUM_HAL_INTERRUPT_RESERVED_115 115
#define CYGNUM_HAL_INTERRUPT_TD_DMA 116
#define CYGNUM_HAL_INTERRUPT_RESERVED_117 117
#define CYGNUM_HAL_INTERRUPT_RESERVED_118 118
#define CYGNUM_HAL_INTERRUPT_RESERVED_119 119
#define CYGNUM_HAL_INTERRUPT_IC_IF_0 120
#define CYGNUM_HAL_INTERRUPT_RESERVED_121 121
#define CYGNUM_HAL_INTERRUPT_RESERVED_122 122
#define CYGNUM_HAL_INTERRUPT_RESERVED_123 123
#define CYGNUM_HAL_INTERRUPT_IC_IF_1 124
#define CYGNUM_HAL_INTERRUPT_RESERVED_125 125
#define CYGNUM_HAL_INTERRUPT_RESERVED_126 126
#define CYGNUM_HAL_INTERRUPT_RESERVED_127 127
#define CYGNUM_HAL_INTERRUPT_I2C_0 128
#define CYGNUM_HAL_INTERRUPT_RESERVED_129 129
#define CYGNUM_HAL_INTERRUPT_RESERVED_130 130
#define CYGNUM_HAL_INTERRUPT_RESERVED_131 131
#define CYGNUM_HAL_INTERRUPT_I2C_1 132
#define CYGNUM_HAL_INTERRUPT_RESERVED_133 133
#define CYGNUM_HAL_INTERRUPT_RESERVED_134 134
#define CYGNUM_HAL_INTERRUPT_RESERVED_135 135
#define CYGNUM_HAL_INTERRUPT_KEY 136
#define CYGNUM_HAL_INTERRUPT_RESERVED_137 137
#define CYGNUM_HAL_INTERRUPT_RESERVED_138 138
#define CYGNUM_HAL_INTERRUPT_RESERVED_139 139
#define CYGNUM_HAL_INTERRUPT_IR_INPUT_0 140
#define CYGNUM_HAL_INTERRUPT_RESERVED_141 141
#define CYGNUM_HAL_INTERRUPT_RESERVED_142 142
#define CYGNUM_HAL_INTERRUPT_RESERVED_143 143
#define CYGNUM_HAL_INTERRUPT_IR_INPUT_1 144
#define CYGNUM_HAL_INTERRUPT_RESERVED_145 145
#define CYGNUM_HAL_INTERRUPT_RESERVED_146 146
#define CYGNUM_HAL_INTERRUPT_RESERVED_147 147
#define CYGNUM_HAL_INTERRUPT_IR_OUTPUT 148
#define CYGNUM_HAL_INTERRUPT_RESERVED_149 149
#define CYGNUM_HAL_INTERRUPT_RESERVED_150 150
#define CYGNUM_HAL_INTERRUPT_RESERVED_151 151
#define CYGNUM_HAL_INTERRUPT_ICAM_0 152
#define CYGNUM_HAL_INTERRUPT_RESERVED_153 153
#define CYGNUM_HAL_INTERRUPT_RESERVED_154 154
#define CYGNUM_HAL_INTERRUPT_RESERVED_155 155
#define CYGNUM_HAL_INTERRUPT_ICAM_1 156
#define CYGNUM_HAL_INTERRUPT_RESERVED_157 157
#define CYGNUM_HAL_INTERRUPT_RESERVED_158 158
#define CYGNUM_HAL_INTERRUPT_RESERVED_159 159
#define CYGNUM_HAL_INTERRUPT_AFE 160
#define CYGNUM_HAL_INTERRUPT_RESERVED_161 161
#define CYGNUM_HAL_INTERRUPT_RESERVED_162 162
#define CYGNUM_HAL_INTERRUPT_RESERVED_163 163
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_0 164
#define CYGNUM_HAL_INTERRUPT_RESERVED_165 165
#define CYGNUM_HAL_INTERRUPT_RESERVED_166 166
#define CYGNUM_HAL_INTERRUPT_RESERVED_167 167
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_1 168
#define CYGNUM_HAL_INTERRUPT_RESERVED_169 169
#define CYGNUM_HAL_INTERRUPT_RESERVED_170 170
#define CYGNUM_HAL_INTERRUPT_RESERVED_171 171
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_2 172
#define CYGNUM_HAL_INTERRUPT_RESERVED_173 173
#define CYGNUM_HAL_INTERRUPT_RESERVED_174 174
#define CYGNUM_HAL_INTERRUPT_RESERVED_175 175
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_3 176
#define CYGNUM_HAL_INTERRUPT_RESERVED_177 177
#define CYGNUM_HAL_INTERRUPT_RESERVED_178 178
#define CYGNUM_HAL_INTERRUPT_RESERVED_179 179
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_4 180
#define CYGNUM_HAL_INTERRUPT_RESERVED_181 181
#define CYGNUM_HAL_INTERRUPT_RESERVED_182 182
#define CYGNUM_HAL_INTERRUPT_RESERVED_183 183
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_5 184
#define CYGNUM_HAL_INTERRUPT_RESERVED_185 185
#define CYGNUM_HAL_INTERRUPT_RESERVED_186 186
#define CYGNUM_HAL_INTERRUPT_RESERVED_187 187
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_6 188
#define CYGNUM_HAL_INTERRUPT_RESERVED_189 189
#define CYGNUM_HAL_INTERRUPT_RESERVED_190 190
#define CYGNUM_HAL_INTERRUPT_RESERVED_191 191
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_7 192
#define CYGNUM_HAL_INTERRUPT_RESERVED_193 193
#define CYGNUM_HAL_INTERRUPT_RESERVED_194 194
#define CYGNUM_HAL_INTERRUPT_RESERVED_195 195
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_8 196
#define CYGNUM_HAL_INTERRUPT_RESERVED_197 197
#define CYGNUM_HAL_INTERRUPT_RESERVED_198 198
#define CYGNUM_HAL_INTERRUPT_RESERVED_199 199
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_9 200
#define CYGNUM_HAL_INTERRUPT_RESERVED_201 201
#define CYGNUM_HAL_INTERRUPT_RESERVED_202 202
#define CYGNUM_HAL_INTERRUPT_RESERVED_203 203
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_10 204
#define CYGNUM_HAL_INTERRUPT_RESERVED_205 205
#define CYGNUM_HAL_INTERRUPT_RESERVED_206 206
#define CYGNUM_HAL_INTERRUPT_RESERVED_207 207
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_11 208
#define CYGNUM_HAL_INTERRUPT_RESERVED_209 209
#define CYGNUM_HAL_INTERRUPT_RESERVED_210 210
#define CYGNUM_HAL_INTERRUPT_RESERVED_211 211
#define CYGNUM_HAL_INTERRUPT_EXTERNAL_12 212
#define CYGNUM_HAL_INTERRUPT_RESERVED_213 213
#define CYGNUM_HAL_INTERRUPT_RESERVED_214 214
#define CYGNUM_HAL_INTERRUPT_RESERVED_215 215
#define CYGNUM_HAL_ISR_MIN 0
#define CYGNUM_HAL_ISR_MAX 215
#define CYGNUM_HAL_ISR_COUNT (3+((CYGNUM_HAL_ISR_MAX+1)/4))
// The vector used by the Real time clock
#define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_TIMER_5
//--------------------------------------------------------------------------
// Interrupt vector translation.
#if !defined(HAL_TRANSLATE_VECTOR) && !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
_index_ = (((_vector_)<=CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR) ? \
(_vector_) : \
(((_vector_)>>2)+CYGNUM_HAL_INTERRUPT_RESERVED_3))
#endif
//--------------------------------------------------------------------------
// AM33 specific version of HAL_INTERRUPT_CONFIGURE
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
CYG_MACRO_START \
if( (_vector_) >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0 ) \
{ \
cyg_uint32 _v_ = _vector_; \
cyg_uint16 _val_ = 0; \
cyg_uint32 _reg_; \
\
/* adjust vector to bit offset in EXTMD */ \
_v_ -= CYGNUM_HAL_INTERRUPT_EXTERNAL_0; \
_v_ >>= 1; \
\
/* set bits according to requirements */ \
if( _up_ ) _val_ |= 1; \
if( !(_level_) ) _val_ |= 2; \
\
/* get EXTMD */ \
_reg_ = *(volatile cyg_uint32 *)&mn10300_interrupt_control[0x200>>1]; \
\
/* clear old value and set new */ \
_reg_ &= ~(3<<_v_); \
_reg_ |= _val_<<_v_; \
\
/* restore EXTMD */ \
*(volatile cyg_uint32 *)&mn10300_interrupt_control[0x200>>1] = _reg_; \
} \
CYG_MACRO_END
#define HAL_INTERRUPT_CONFIGURE_DEFINED
//--------------------------------------------------------------------------
// Timer control registers.
// On the AM33 we use timers 4 and 5
#define TIMER4_CR 0xd40030a0
#define TIMER4_BR 0xd4003090
#define TIMER4_MD 0xd4003080
#define TIMER5_CR 0xd40030a2
#define TIMER5_BR 0xd4003092
#define TIMER5_MD 0xd4003082
//--------------------------------------------------------------------------
// Clock control.
extern cyg_uint32 __hal_period__;
#define HAL_CLOCK_INITIALIZE( _period_ ) \
{ \
volatile cyg_uint16 *timer4_br = (cyg_uint16 *)TIMER4_BR; \
volatile cyg_uint8 *timer4_md = (cyg_uint8 *)TIMER4_MD; \
volatile cyg_uint16 *timer5_br = (cyg_uint16 *)TIMER5_BR; \
volatile cyg_uint8 *timer5_md = (cyg_uint8 *)TIMER5_MD; \
\
/* Set timers 4 and 5 into cascade mode */ \
\
*timer5_br = (_period_)>>16; \
\
*timer5_md = 0x40; \
*timer5_md = 0x83; \
\
*timer4_br = (_period_)&0x0000FFFF; \
\
*timer4_md = 0x40; \
*timer4_md = 0x80; \
\
__hal_period__ = _period_; \
}
#define HAL_CLOCK_RESET( _vector_, _period_ )
#define HAL_CLOCK_READ( _pvalue_ ) \
{ \
volatile cyg_uint16 *timer4_cr = (cyg_uint16 *)TIMER4_CR; \
volatile cyg_uint16 *timer5_cr = (cyg_uint16 *)TIMER5_CR; \
\
cyg_uint16 t5; \
cyg_uint16 t4; \
\
/* Loop reading the two timers until we can read t5 twice */ \
/* with the same value. This avoids getting silly times if */ \
/* the timers carry between reading the two regs. */ \
do { \
t5 = *timer5_cr; \
t4 = *timer4_cr; \
} while( t5 != *timer5_cr ); \
\
*(_pvalue_) = __hal_period__ - ((t5<<16) + t4); \
}
externC void hal_delay_us(cyg_int32 usecs);
#define HAL_DELAY_US(n) hal_delay_us(n);
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_VAR_INTR_H
// End of var_intr.h
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