📄 hal_arch.h
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_regval_[2] = (_regs_)->d2; \
_regval_[3] = (_regs_)->d3; \
_regval_[4] = (_regs_)->a0; \
_regval_[5] = (_regs_)->a1; \
_regval_[6] = (_regs_)->a2; \
_regval_[7] = (_regs_)->a3; \
\
_regval_[8] = (_regs_)->sp; \
_regval_[9] = (_regs_)->pc; \
_regval_[10] = (_regs_)->mdr; \
_regval_[11] = (_regs_)->psw; \
\
_regval_[12] = (_regs_)->lar; \
_regval_[13] = (_regs_)->lir; \
HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ); \
}
#else
#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \
{ \
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
\
_regval_[0] = (_regs_)->d0; \
_regval_[1] = (_regs_)->d1; \
_regval_[2] = (_regs_)->d2; \
_regval_[3] = (_regs_)->d3; \
_regval_[4] = (_regs_)->a0; \
_regval_[5] = (_regs_)->a1; \
_regval_[6] = (_regs_)->a2; \
_regval_[7] = (_regs_)->a3; \
\
_regval_[8] = (_regs_)->sp = (CYG_ADDRWORD)(_regs_) + \
sizeof(HAL_SavedRegisters); \
_regval_[9] = (_regs_)->pc; \
_regval_[10] = (_regs_)->mdr; \
_regval_[11] = (_regs_)->psw; \
\
_regval_[12] = (_regs_)->lar; \
_regval_[13] = (_regs_)->lir; \
HAL_GET_GDB_EXTRA_REGISTERS( _regval_, _regs_ ); \
}
#endif
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
//
// The CYGMON version should differ by also handling SP and PSW
// since we will be using a different stack.
#ifdef CYGPKG_CYGMON
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
{ \
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
\
(_regs_)->d0 = _regval_[0]; \
(_regs_)->d1 = _regval_[1]; \
(_regs_)->d2 = _regval_[2]; \
(_regs_)->d3 = _regval_[3]; \
(_regs_)->a0 = _regval_[4]; \
(_regs_)->a1 = _regval_[5]; \
(_regs_)->a2 = _regval_[6]; \
(_regs_)->a3 = _regval_[7]; \
\
(_regs_)->sp = _regval_[8]; \
(_regs_)->pc = _regval_[9]; \
(_regs_)->mdr = _regval_[10]; \
(_regs_)->psw = _regval_[11]; \
\
(_regs_)->lar = _regval_[12]; \
(_regs_)->lir = _regval_[13]; \
\
HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ); \
}
#else
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
{ \
CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
\
(_regs_)->d0 = _regval_[0]; \
(_regs_)->d1 = _regval_[1]; \
(_regs_)->d2 = _regval_[2]; \
(_regs_)->d3 = _regval_[3]; \
(_regs_)->a0 = _regval_[4]; \
(_regs_)->a1 = _regval_[5]; \
(_regs_)->a2 = _regval_[6]; \
(_regs_)->a3 = _regval_[7]; \
\
(_regs_)->pc = _regval_[9]; \
(_regs_)->mdr = _regval_[10]; \
\
(_regs_)->lar = _regval_[12]; \
(_regs_)->lir = _regval_[13]; \
\
/* We do not allow the SP or PSW to be set. Changing the SP will \
* mess up the saved state. No PSW is saved on thread context \
* switches, so there is nowhere to save it to. \
*/ \
\
HAL_SET_GDB_EXTRA_REGISTERS( _regs_, _regval_ ); \
}
#endif
//-------------------------------------------------------------------------
// HAL setjmp
// Note: These definitions are repeated in context.S. If changes are required
// remember to update both sets.
#define CYGARC_JMP_BUF_SP 0
#define CYGARC_JMP_BUF_D2 1
#define CYGARC_JMP_BUF_D3 2
#define CYGARC_JMP_BUF_A2 3
#define CYGARC_JMP_BUF_A3 4
#define CYGARC_JMP_BUF_LR 5
#define CYGARC_JMP_BUF_SIZE 6
typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
externC int hal_setjmp(hal_jmp_buf env);
externC void hal_longjmp(hal_jmp_buf env, int val);
//-------------------------------------------------------------------------
// Idle thread code.
// This macro is called in the idle thread loop, and gives the HAL the
// chance to insert code. Typical idle thread behaviour might be to halt the
// processor.
externC void hal_idle_thread_action(cyg_uint32 loop_count);
#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
//-----------------------------------------------------------------------------
// Minimal and sensible stack sizes: the intention is that applications
// will use these to provide a stack size in the first instance prior to
// proper analysis. Idle thread stack should be this big.
// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
// We define quite large stack needs for SPARClite, for it requires 576
// bytes (144 words) to process an interrupt and thread-switch, and
// momentarily, but needed in case of recursive interrupts, it needs 208
// words - if a sequence of saves to push out other regsets is interrupted.
// This is not a config option because it should not be adjusted except
// under "enough rope" sort of disclaimers.
// Worst case stack frame size: return link + 4 args + 4 pushed registers.
#define CYGNUM_HAL_STACK_FRAME_SIZE (40)
// Stack needed for a context switch:
#define CYGNUM_HAL_STACK_CONTEXT_SIZE (60)
// Interrupt + call to ISR, interrupt_end() and the DSR
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (128)
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
// An interrupt stack which is large enough for all possible interrupt
// conditions (and only used for that purpose) exists. "User" stacks
// can be much smaller
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \
CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \
CYGNUM_HAL_STACK_FRAME_SIZE*16)
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (2048)
#else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
// No separate interrupt stack exists. Make sure all threads contain
// a stack sufficiently large.
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096)
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096)
#endif
//--------------------------------------------------------------------------
// Macros for switching context between two eCos instances (jump from
// code in ROM to code in RAM or vice versa).
#define CYGARC_HAL_SAVE_GP()
#define CYGARC_HAL_RESTORE_GP()
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_HAL_ARCH_H
// EOF hal_arch.h
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