var_cache.h

开放源码实时操作系统源码.

    register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
    register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
    register CYG_WORD _size_ = (_asize_);                                               \
    for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )                   \
      asm volatile (" cache %0, 0(%1)"                                                  \
                    :                                                                   \
                    : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_FETCH_AND_LOCK)),         \
                      "r"(_addr_));                                                     \
    CYG_MACRO_END

// Undo a previous lock operation
#define HAL_DCACHE_UNLOCK_DEFINED
#define HAL_DCACHE_UNLOCK(_base_, _asize_)                                              \
    CYG_MACRO_START                                                                     \
    register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
    register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
    register CYG_WORD _size_ = (_asize_);                                               \
    for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )                   \
      asm volatile (" cache %0, 0(%1)"                                                  \
                    :                                                                   \
                    : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)),         \
                      "r"(_addr_));                                                     \
    CYG_MACRO_END

// Unlock entire cache
#define HAL_DCACHE_UNLOCK_ALL_DEFINED
#define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)


//-----------------------------------------------------------------------------
// Data cache line control

// Allocate cache lines for the given address range without reading its
// contents from memory.
//#define HAL_DCACHE_ALLOCATE( _base_ , _asize_ )

// Write dirty cache lines to memory and invalidate the cache entries
// for the given address range.
#define HAL_DCACHE_FLUSH_DEFINED
#if HAL_DCACHE_WRITETHRU_MODE == 1
// No need to flush a writethrough cache
#define HAL_DCACHE_FLUSH( _base_ , _asize_ )
#else
#error HAL_DCACHE_FLUSH undefined for MIPS32 writeback cache
#endif

// Write dirty cache lines to memory for the given address range.
#define HAL_DCACHE_STORE_DEFINED
#if HAL_DCACHE_WRITETHRU_MODE == 1
// No need to store a writethrough cache
#define HAL_DCACHE_STORE( _base_ , _asize_ )
#else
#error HAL_DCACHE_STORE undefined for MIPS32 writeback cache
#endif

// Invalidate cache lines in the given range without writing to memory.
#define HAL_DCACHE_INVALIDATE_DEFINED
#define HAL_DCACHE_INVALIDATE( _base_ , _asize_ )                                       \
    CYG_MACRO_START                                                                     \
    register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
    register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
    register CYG_WORD _size_ = (_asize_);                                               \
    for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )                   \
      asm volatile (" cache %0, 0(%1)"                                                  \
                    :                                                                   \
                    : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)),         \
                      "r"(_addr_));                                                       \
    CYG_MACRO_END






//-----------------------------------------------------------------------------
// Global control of Instruction cache

// Invalidate the entire cache
#define HAL_ICACHE_INVALIDATE_ALL_DEFINED
#define HAL_ICACHE_INVALIDATE_ALL()                                                     \
    CYG_MACRO_START                                                                     \
    register volatile CYG_BYTE *addr;                                                   \
    HAL_CLEAR_TAGLO();                                                                  \
    HAL_CLEAR_TAGHI();                                                                  \
    for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE;                                    \
         addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_ICACHE_SIZE);                \
         addr += HAL_ICACHE_LINE_SIZE )                                                 \
    {                                                                                   \
        asm volatile (" cache %0, 0(%1)"                                                \
                      :                                                                 \
                      : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_INDEX_STORE_TAG)),      \
                        "r"(addr));                                                     \
    }                                                                                   \
    CYG_MACRO_END

// Synchronize the contents of the cache with memory.
extern void hal_icache_sync(void);
#define HAL_ICACHE_SYNC_DEFINED
#define HAL_ICACHE_SYNC() hal_icache_sync()

// Set the instruction cache refill burst size
//#define HAL_ICACHE_BURST_SIZE(_asize_)

// Load the contents of the given address range into the data cache
// and then lock the cache so that it stays there.
#define HAL_ICACHE_LOCK_DEFINED
#define HAL_ICACHE_LOCK(_base_, _asize_)                                                \
    CYG_MACRO_START                                                                     \
    register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
    register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
    register CYG_WORD _size_ = (_asize_);                                               \
    for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )                   \
      asm volatile (" cache %0, 0(%1)"                                                  \
                    :                                                                   \
                    : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_FETCH_AND_LOCK)),         \
                      "r"(_addr_));                                                     \
    CYG_MACRO_END

// Undo a previous lock operation
#define HAL_ICACHE_UNLOCK_DEFINED
#define HAL_ICACHE_UNLOCK(_base_, _asize_)                                              \
    CYG_MACRO_START                                                                     \
    register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
    register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
    register CYG_WORD _size_ = (_asize_);                                               \
    for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )                   \
      asm volatile (" cache %0, 0(%1)"                                                  \
                    :                                                                   \
                    : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)),         \
                      "r"(_addr_));                                                     \
    CYG_MACRO_END

// Unlock entire cache
#define HAL_ICACHE_UNLOCK_ALL_DEFINED
#define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0,HAL_ICACHE_SIZE)

//-----------------------------------------------------------------------------
// Instruction cache line control

// Invalidate cache lines in the given range without writing to memory.
#define HAL_ICACHE_INVALIDATE_DEFINED
#define HAL_ICACHE_INVALIDATE( _base_ , _asize_ )                                       \
    CYG_MACRO_START                                                                     \
    register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
    register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
    register CYG_WORD _size_ = (_asize_);                                               \
    for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )                   \
      asm volatile (" cache %0, 0(%1)"                                                  \
                    :                                                                   \
                    : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)),         \
                      "r"(_addr_));                                                     \
    CYG_MACRO_END

//-----------------------------------------------------------------------------
#endif // ifndef CYGONCE_IMP_CACHE_H
// End of imp_cache.h