📄 plf_io.h
字号:
nop; \
nop
# define DEBUG_LED_IMM(val) \
li k0, HAL_DISPLAY_LEDBAR; \
li k1, val; \
sw k1, 0(k0)
# define DEBUG_LED_REG(reg) \
li k0, HAL_DISPLAY_LEDBAR; \
sw reg, 0(k0)
# define DEBUG_HEX_DISPLAY_IMM(val) \
li k0, HAL_DISPLAY_ASCIIWORD; \
li k1, val; \
sw k1, 0(k0)
# define DEBUG_HEX_DISPLAY_REG(reg) \
li k0, HAL_DISPLAY_ASCIIWORD; \
sw reg, 0(k0)
# define DEBUG_DELAY() \
li k0, 0x20000; \
0: sub k0, k0, 1; \
bnez k0, 0b; \
nop
#else
# define DEBUG_ASCII_DISPLAY(register, character) \
*(register) = character
# define DEBUG_LED_IMM(val) \
*HAL_DISPLAY_LEDBAR = val
# define DEBUG_HEX_DISPLAY_IMM(val) \
*HAL_DISPLAY_ASCIIWORD = val
# define DEBUG_DELAY() \
{ \
volatile int i = 0x20000; \
while (--i) ; \
}
# define DEBUG_DISPLAY(str) \
{ \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS0, str[0]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS1, str[1]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS2, str[2]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS3, str[3]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS4, str[4]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS5, str[5]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS6, str[6]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS7, str[7]); \
}
#define HAL_GALILEO_PUTREG(x,y) \
(*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_MALTA_CONTROLLER_BASE) + (x))) = (y))
#define HAL_GALILEO_GETREG(x) \
(*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_MALTA_CONTROLLER_BASE) + (x))))
extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint32 val);
extern void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint16 val);
extern void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint8 val);
// Initialize the PCI bus.
externC void cyg_hal_plf_pci_init(void);
#define HAL_PCI_INIT() cyg_hal_plf_pci_init()
// leave gap at start of IO and mem for southbridge which is beyond standards
// and not only ignores writes to the BAR, but also does not advertise use of
// any IO/memory space. That is, southbridge is hardwired at 0x18000000
// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY (HAL_MALTA_PCI_MEM0_BASE + 0x20000)
#define HAL_PCI_ALLOC_BASE_IO 0x10000
// This is where the PCI spaces are mapped in the CPU's address space.
//
#define HAL_PCI_PHYSICAL_MEMORY_BASE CYGARC_UNCACHED_ADDRESS(0)
#define HAL_PCI_PHYSICAL_IO_BASE CYGARC_UNCACHED_ADDRESS(HAL_MALTA_PCI_IO_BASE)
// Read a value from the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_byte((__bus), (__devfn), (__offset))
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_word((__bus), (__devfn), (__offset))
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_dword((__bus), (__devfn), (__offset))
// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val))
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val))
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val))
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
CYG_MACRO_START \
cyg_uint8 __req; \
HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
if (0 != __req) { \
/* Interrupt assignment as Galileo sees them. */ \
/* (From Malta User's Manual, 6.1 PCI Bus) */ \
CYG_ADDRWORD __translation[4] = { \
CYGNUM_HAL_INTERRUPT_PCI_AB, /* INTB# */ \
CYGNUM_HAL_INTERRUPT_PCI_CD, /* INTC# */ \
CYGNUM_HAL_INTERRUPT_PCI_CD, /* INTD# */ \
CYGNUM_HAL_INTERRUPT_PCI_AB}; /* INTA# */ \
\
/* The PCI lines from the different slots are wired like this */ \
/* on the PCI backplane: */ \
/* PCI_AB PCI_AB PCI_CD PCI_CD */ \
/* AMD PCnet INTA# */ \
/* I/O Slot 1 INTA# INTB# INTC# INTD# */ \
/* I/O Slot 2 INTD# INTA# INTB# INTC# */ \
/* I/O Slot 3 INTC# INTD# INTA# INTB# */ \
/* I/O Slot 4 INTB# INTC# INTD# INTA# */ \
/* */ \
/* Devsel signals are wired to, resulting in device IDs: */ \
/* AMD PCnet AD21 / dev 11 [(11+1)&3 = 0] */ \
/* I/O Slot 1 AD28 / dev 18 [(18+1)&3 = 3] */ \
/* I/O Slot 2 AD29 / dev 19 [(19+1)&3 = 0] */ \
/* I/O Slot 3 AD30 / dev 20 [(20+1)&3 = 1] */ \
/* I/O Slot 4 AD31 / dev 21 [(21+1)&3 = 2] */ \
\
/* For some reason the Ethernet device comes in on interrupt */ \
/* 11 rather than interrupt 16. */ \
if( (__bus)==0 && (__devfn)==0x58 ) \
__vec = CYGNUM_HAL_INTERRUPT_11; \
else __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
__valid = true; \
} else { \
/* Device will not generate interrupt requests. */ \
__valid = false; \
} \
CYG_MACRO_END
// Galileo GT64120 on MIPS MALTA requires special processing.
// First, it will hang when accessing device 31 on the local bus.
// Second, we need to ignore the GT64120 so we can set it up
// outside the generic PCI library.
#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \
((__bus) == 0 && ((__dev) == 0 || (__dev) == 31))
// Bus address translation macros
#define HAL_PCI_CPU_TO_BUS(__cpu_addr, __bus_addr) \
CYG_MACRO_START \
(__bus_addr) = CYGARC_PHYSICAL_ADDRESS((cyg_uint32)__cpu_addr); \
CYG_MACRO_END
#define HAL_PCI_BUS_TO_CPU(__bus_addr, __cpu_addr) \
CYG_MACRO_START \
(__cpu_addr) = CYGARC_UNCACHED_ADDRESS(__bus_addr); \
CYG_MACRO_END
// IDE interface macros
//
#define HAL_IDE_NUM_CONTROLLERS 2
// Initialize the IDE controller(s).
externC int cyg_hal_plf_ide_init(void);
#define HAL_IDE_INIT() cyg_hal_plf_ide_init()
#define HAL_IDE_READ_UINT8( __ctlr, __regno, __val ) \
__val = *HAL_REG8(((__ctlr) ? HAL_PIIX4_IDE_SEC_CMD : HAL_PIIX4_IDE_PRI_CMD) + (__regno))
#define HAL_IDE_READ_UINT16( __ctlr, __regno, __val ) \
__val = *HAL_REG16(((__ctlr) ? HAL_PIIX4_IDE_SEC_CMD : HAL_PIIX4_IDE_PRI_CMD) + (__regno))
#define HAL_IDE_READ_ALTSTATUS( __ctlr, __val ) \
__val = *HAL_REG16(((__ctlr) ? HAL_PIIX4_IDE_SEC_CTL : HAL_PIIX4_IDE_PRI_CTL) + 2)
#define HAL_IDE_WRITE_UINT8( __ctlr, __regno, __val ) \
*HAL_REG8( ((__ctlr) ? HAL_PIIX4_IDE_SEC_CMD : HAL_PIIX4_IDE_PRI_CMD) + (__regno)) = (__val)
#define HAL_IDE_WRITE_UINT16( __ctlr, __regno, __val ) \
*HAL_REG16( ((__ctlr) ? HAL_PIIX4_IDE_SEC_CMD : HAL_PIIX4_IDE_PRI_CMD) + (__regno)) = (__val)
#define HAL_IDE_WRITE_CONTROL( __ctlr, __val ) \
*HAL_REG8( ((__ctlr) ? HAL_PIIX4_IDE_SEC_CTL : HAL_PIIX4_IDE_PRI_CTL) + 2) = (__val)
#endif
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -