📄 plf_io.h
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/* Galileo Memory Controller registers */
#define HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR BIT20
#define HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS BIT14
#define HAL_GALILEO_CPU_DECODE_SHIFT 21
#define HAL_GALILEO_DEV_DECODE_SHIFT 20
#define HAL_GALILEO_SDRAM_SRAS_TO_SCAS_DELAY_3C BIT10
#define HAL_GALILEO_SDRAM_WIDTH_64BIT BIT6
#define HAL_GALILEO_SDRAM_SRAS_PRECHARGE_3C BIT3
#define HAL_GALILEO_SDRAM_BANK0_CASLAT_2 BIT0
#define HAL_GALILEO_SDRAM_BANK0_SZ_64M BIT11
#define HAL_GALILEO_SDRAM_NUM_BANKS_4 BIT5
#define HAL_GALILEO_SDRAM_BANK0_PARITY BIT8
#define HAL_GALILEO_SDRAM_CFG_RAM_WIDTH BIT15
#define HAL_GALILEO_PCI0_CONFIG_ADDR_ConfigEn BIT31
#define HAL_GALILEO_PCI0_STATUS_COMMAND_REGNUM 0x04
#define HAL_GALILEO_PCI0_BIST_REGNUM 0x0C
#define HAL_GALILEO_PCI0_SCS32_BASE_REGNUM 0x14
#define HAL_GALILEO_PCI0_CONFIG_IOEn 0x1
#define HAL_GALILEO_PCI0_CONFIG_MEMEn 0x2
#define HAL_GALILEO_PCI0_CONFIG_MasEn 0x4
#define HAL_GALILEO_PCI0_CONFIG_SErrEn 0x100
#define HAL_GALILEO_PCI0_LAT_TIMER_VAL 0x800
#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_VALUE 0x00ffffff
#define HAL_GALILEO_SDRAM_BANK0_OFFSET 0x44c
#define HAL_GALILEO_SDRAM_BANK2_OFFSET 0x454
#define HAL_GALILEO_SDRAM_CONFIG_OFFSET 0x448
#define HAL_GALILEO_SCS10_LD_OFFSET 0x008
#define HAL_GALILEO_SCS10_HD_OFFSET 0x010
#define HAL_GALILEO_SCS32_LD_OFFSET 0x018
#define HAL_GALILEO_SCS32_HD_OFFSET 0x020
#define HAL_GALILEO_CS20_LD_OFFSET 0x028
#define HAL_GALILEO_CS20_HD_OFFSET 0x030
#define HAL_GALILEO_PCIIO_LD_OFFSET 0x048
#define HAL_GALILEO_PCIIO_HD_OFFSET 0x050
#define HAL_GALILEO_PCIMEM0_LD_OFFSET 0x058
#define HAL_GALILEO_PCIMEM0_HD_OFFSET 0x060
#define HAL_GALILEO_PCIMEM1_LD_OFFSET 0x080
#define HAL_GALILEO_PCIMEM1_HD_OFFSET 0x088
#define HAL_GALILEO_PCI1IO_LD_OFFSET 0x090
#define HAL_GALILEO_PCI1IO_HD_OFFSET 0x098
#define HAL_GALILEO_PCI1MEM0_LD_OFFSET 0x0a0
#define HAL_GALILEO_PCI1MEM0_HD_OFFSET 0x0a8
#define HAL_GALILEO_PCI1MEM1_LD_OFFSET 0x0b0
#define HAL_GALILEO_PCI1MEM1_HD_OFFSET 0x0b8
#define HAL_GALILEO_PCI_IO_REMAP 0x0f0
#define HAL_GALILEO_SCS0_LD_OFFSET 0x400
#define HAL_GALILEO_SCS0_HD_OFFSET 0x404
#define HAL_GALILEO_SCS1_LD_OFFSET 0x408
#define HAL_GALILEO_SCS1_HD_OFFSET 0x40c
#define HAL_GALILEO_SCS2_LD_OFFSET 0x410
#define HAL_GALILEO_SCS2_HD_OFFSET 0x414
#define HAL_GALILEO_SCS3_LD_OFFSET 0x418
#define HAL_GALILEO_SCS3_HD_OFFSET 0x41c
#define HAL_GALILEO_CS0_LD_OFFSET 0x420
#define HAL_GALILEO_CS0_HD_OFFSET 0x424
#define HAL_GALILEO_CS1_LD_OFFSET 0x428
#define HAL_GALILEO_CS1_HD_OFFSET 0x42c
#define HAL_GALILEO_CS2_LD_OFFSET 0x430
#define HAL_GALILEO_CS2_HD_OFFSET 0x434
// GALILEO PCI Internal
#define HAL_GALILEO_PCI_INTERNAL_COMMAND_OFFSET 0xC00
#define HAL_GALILEO_PCI0_TIMEOUT_RETRY_OFFSET 0xc04
#define HAL_GALILEO_PCI0_SCS10_SIZE_OFFSET 0xc08
#define HAL_GALILEO_PCI0_SCS32_SIZE_OFFSET 0xc0c
#define HAL_GALILEO_PCI0_SCS20_SIZE_OFFSET 0xc10
#define HAL_GALILEO_PCI0_CS3_SIZE_OFFSET 0xc14
#define HAL_GALILEO_BAR_ENA_OFFSET 0xc3c
# define HAL_GALILEO_BAR_ENA_SWCS3 (1 << 0)
# define HAL_GALILEO_BAR_ENA_SWCS32 (1 << 1)
# define HAL_GALILEO_BAR_ENA_SWCS10 (1 << 2)
# define HAL_GALILEO_BAR_ENA_IO (1 << 3)
# define HAL_GALILEO_BAR_ENA_MEM (1 << 4)
# define HAL_GALILEO_BAR_ENA_CS3 (1 << 5)
# define HAL_GALILEO_BAR_ENA_CS20 (1 << 6)
# define HAL_GALILEO_BAR_ENA_SCS32 (1 << 7)
# define HAL_GALILEO_BAR_ENA_SCS10 (1 << 8)
#define HAL_GALILEO_PCI0_CONFIG_ADDR_OFFSET 0xcf8
# define HAL_GALILEO_PCI0_CONFIG_ADDR_ENABLE (1 << 31)
#define HAL_GALILEO_PCI0_CONFIG_DATA_OFFSET 0xcfc
// GALILEO Interrupts
#define HAL_GALILEO_IRQ_CAUSE_OFFSET 0xc18
# define HAL_GALILEO_IRQCAUSE_INTSUM (1 << 0)
# define HAL_GALILEO_IRQCAUSE_MEMOUT (1 << 1)
# define HAL_GALILEO_IRQCAUSE_DMAOUT (1 << 2)
# define HAL_GALILEO_IRQCAUSE_CPUOUT (1 << 3)
# define HAL_GALILEO_IRQCAUSE_DMA0 (1 << 4)
# define HAL_GALILEO_IRQCAUSE_DMA1 (1 << 5)
# define HAL_GALILEO_IRQCAUSE_DMA2 (1 << 6)
# define HAL_GALILEO_IRQCAUSE_DMA3 (1 << 7)
# define HAL_GALILEO_IRQCAUSE_T0 (1 << 8)
# define HAL_GALILEO_IRQCAUSE_T1 (1 << 9)
# define HAL_GALILEO_IRQCAUSE_T2 (1 << 10)
# define HAL_GALILEO_IRQCAUSE_T3 (1 << 11)
# define HAL_GALILEO_IRQCAUSE_MASRD (1 << 12)
# define HAL_GALILEO_IRQCAUSE_SLVWR (1 << 13)
# define HAL_GALILEO_IRQCAUSE_MASWR (1 << 14)
# define HAL_GALILEO_IRQCAUSE_SLVRD (1 << 15)
# define HAL_GALILEO_IRQCAUSE_AERR (1 << 16)
# define HAL_GALILEO_IRQCAUSE_MERR (1 << 17)
# define HAL_GALILEO_IRQCAUSE_MASABT (1 << 18)
# define HAL_GALILEO_IRQCAUSE_TARABT (1 << 19)
# define HAL_GALILEO_IRQCAUSE_RETRY (1 << 20)
# define HAL_GALILEO_IRQCAUSE_CPUSUM (1 << 30)
# define HAL_GALILEO_IRQCAUSE_PCISUM (1 << 31)
#define HAL_GALILEO_HIRQ_CAUSE_OFFSET 0xc98
#define HAL_GALILEO_CPUIRQ_MASK_OFFSET 0xc1c
#define HAL_GALILEO_CPUHIRQ_MASK_OFFSET 0xc9c
#define HAL_I2CFPGA_BASE 0x1f000b00
#define HAL_I2CFPGA_INP 0x00
#define HAL_I2CFPGA_OE 0x08
#define HAL_I2CFPGA_OUT 0x10
#define HAL_I2CFPGA_SEL 0x18
#define HAL_I2CFPGA_SEL_FPGA 0x00000001
#define HAL_I2CFPGA_SEL_SB 0x00000000
#define HAL_I2CFPGA_OE_SCL_OUT 0x00000002
#define HAL_I2CFPGA_OE_SCL_TRI 0x00000000
#define HAL_I2CFPGA_OE_SDA_OUT 0x00000001
#define HAL_I2CFPGA_OE_SDA_TRI 0x00000000
#define HAL_I2CFPGA_OUT_SCL_HIGH 0x00000002
#define HAL_I2CFPGA_OUT_SCL_LOW 0x00000000
#define HAL_I2CFPGA_OUT_SDA_HIGH 0x00000001
#define HAL_I2CFPGA_OUT_SDA_LOW 0x00000000
#define HAL_I2CFPGA_IN_SDA_MASK 0x00000001
#define HAL_I2CFPGA_OUT_SDA_ACK 0x00000000
#define HAL_I2CFPGA_OUT_SDA_NACK 0x00000001
#define HAL_I2CFPGA_OUT_SDA_WAIT_ACK 0x00000001
#define HAL_I2C_WRITE 0x00
#define HAL_I2C_READ 0x01
#define HAL_I2C_SPD_ADDRESS 0xa0
#define HAL_I2C_COUT_DOUT (HAL_I2CFPGA_OE_SCL_OUT|HAL_I2CFPGA_OE_SDA_OUT)
#define HAL_I2C_COUT_DIN (HAL_I2CFPGA_OE_SCL_OUT|HAL_I2CFPGA_OE_SDA_TRI)
#define HAL_I2C_CIN_DIN (HAL_I2CFPGA_OE_SCL_TRI|HAL_I2CFPGA_OE_SDA_TRI)
#define HAL_I2C_CHIGH_DHIGH (HAL_I2CFPGA_OUT_SCL_HIGH|HAL_I2CFPGA_OUT_SDA_HIGH)
#define HAL_I2C_CHIGH_DLOW (HAL_I2CFPGA_OUT_SCL_HIGH|HAL_I2CFPGA_OUT_SDA_LOW)
#define HAL_I2C_CLOW_DLOW (HAL_I2CFPGA_OUT_SCL_LOW|HAL_I2CFPGA_OUT_SDA_LOW)
#define HAL_I2C_CLOW_DHIGH (HAL_I2CFPGA_OUT_SCL_LOW|HAL_I2CFPGA_OUT_SDA_HIGH)
#define HAL_SPD_GET_NUM_ROW_BITS 3
#define HAL_SPD_GET_NUM_COL_BITS 4
#define HAL_SPD_GET_NUM_MODULE_BANKS 5
#define HAL_SPD_GET_SDRAM_WIDTH 6
#define HAL_SPD_GET_CONFIG_TYPE 11
#define HAL_SPD_GET_REFRESH_RATE 12
#define HAL_SPD_GET_ERROR_CHECK_WIDTH 14
#define HAL_SPD_GET_BURST_LENGTH 16
#define HAL_SPD_GET_NUM_DEVICE_BANKS 17
#define HAL_SPD_GET_CAS_LAT 18
#define HAL_SPD_GET_ROW_DENSITY 31
#define HAL_SPD_CONFIG_TYPE_PARITY BIT0
#define HAL_SPD_CONFIG_TYPE_ECC BIT1
#define HAL_SPD_REFRESH_RATE_125 5
#define HAL_SPD_REFRESH_RATE_62_5 4
#define HAL_SPD_REFRESH_RATE_31_3 3
#define HAL_SPD_REFRESH_RATE_15_625 0
#define HAL_SPD_REFRESH_RATE_7_8 2
#define HAL_SPD_REFRESH_RATE_3_9 1
#define HAL_SPD_REFRESH_COUNTER_125 (125*2)
#define HAL_SPD_REFRESH_COUNTER_62_5 (62*2)
#define HAL_SPD_REFRESH_COUNTER_31_3 (31*2)
#define HAL_SPD_REFRESH_COUNTER_15_625 (15*2)
#define HAL_SPD_REFRESH_COUNTER_7_8 (7*2)
#define HAL_SPD_REFRESH_COUNTER_3_9 (3*2)
/* Malta Display Registers */
#define HAL_DISPLAY_BASE (HAL_MALTA_REGISTER_BASE + 0x400)
#define HAL_DISPLAY_LEDGREEN_OFFSET 0x00
#define HAL_DISPLAY_LEDBAR_OFFSET 0x08
#define HAL_DISPLAY_ASCIIWORD_OFFSET 0x10
#define HAL_DISPLAY_ASCIIPOS0_OFFSET 0x18
#define HAL_DISPLAY_ASCIIPOS1_OFFSET 0x20
#define HAL_DISPLAY_ASCIIPOS2_OFFSET 0x28
#define HAL_DISPLAY_ASCIIPOS3_OFFSET 0x30
#define HAL_DISPLAY_ASCIIPOS4_OFFSET 0x38
#define HAL_DISPLAY_ASCIIPOS5_OFFSET 0x40
#define HAL_DISPLAY_ASCIIPOS6_OFFSET 0x48
#define HAL_DISPLAY_ASCIIPOS7_OFFSET 0x50
#define HAL_DISPLAY_LEDGREEN HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDGREEN_OFFSET)
#define HAL_DISPLAY_LEDBAR HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDBAR_OFFSET)
#define HAL_DISPLAY_ASCIIWORD HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIWORD_OFFSET)
#define HAL_DISPLAY_ASCIIPOS0 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS0_OFFSET)
#define HAL_DISPLAY_ASCIIPOS1 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS1_OFFSET)
#define HAL_DISPLAY_ASCIIPOS2 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS2_OFFSET)
#define HAL_DISPLAY_ASCIIPOS3 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS3_OFFSET)
#define HAL_DISPLAY_ASCIIPOS4 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS4_OFFSET)
#define HAL_DISPLAY_ASCIIPOS5 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS5_OFFSET)
#define HAL_DISPLAY_ASCIIPOS6 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS6_OFFSET)
#define HAL_DISPLAY_ASCIIPOS7 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS7_OFFSET)
#ifdef __ASSEMBLER__
# define DEBUG_ASCII_DISPLAY(register, character) \
li k0, CYGARC_UNCACHED_ADDRESS(register); \
li k1, character; \
sw k1, 0(k0); \
nop; \
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