plf_io.h

开放源码实时操作系统源码.

#ifndef CYGONCE_PLF_IO_H
#define CYGONCE_PLF_IO_H

//=============================================================================
//
//      plf_io.h
//
//      Platform specific IO support
//
//=============================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//=============================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    dmoseley
// Contributors: dmoseley, jskov
// Date:         2001-03-20
// Purpose:      Malta platform IO support
// Description: 
// Usage:        #include <cyg/hal/plf_io.h>
//
//####DESCRIPTIONEND####
//
//=============================================================================

#include <pkgconf/hal.h>
#include <cyg/hal/hal_misc.h>
#include <cyg/hal/hal_arch.h>
#include <cyg/hal/plf_intr.h>

#ifdef __ASSEMBLER__
#define HAL_REG(x)              x
#define HAL_REG8(x)             x
#define HAL_REG16(x)            x
#else
#define HAL_REG(x)              (volatile CYG_WORD *)(x)
#define HAL_REG8(x)             (volatile CYG_BYTE *)(x)
#define HAL_REG16(x)            (volatile CYG_WORD16 *)(x)
#endif

//-----------------------------------------------------------------------------

/* Malta Memory Definitions */
#define HAL_MALTA_RAM_BASE                      0x00000000
#define HAL_MALTA_PCI_MEM0_BASE                 0x08000000
#define HAL_MALTA_PCI_MEM0_SIZE                 0x08000000  // 128 MB
#define HAL_MALTA_PCI_MEM1_BASE                 0x10000000
#define HAL_MALTA_PCI_MEM1_SIZE                 0x08000000  // 128 MB

#define HAL_MALTA_PCI_IO_BASE                   0x18000000
#define HAL_MALTA_PCI_IO_SIZE                   0x03d00000  //  62 MB
#define HAL_MALTA_CONTROLLER_BASE               0x1BE00000
#define HAL_MALTA_CONTROLLER_BASE_ISD_CONFIG    (HAL_MALTA_CONTROLLER_BASE >> 21)
#define HAL_MALTA_FLASH_BASE                    0x1E000000
#define HAL_MALTA_FLASH_SIZE                    SZ_4M
#define HAL_MALTA_MAX_BANKSIZE                  SZ_128M

#define HAL_MALTA_NULL_DEVNUM                   0x0
#define HAL_MALTA_MEMERROR                      1

// PCI registers
#define _PIIX4_PCI_ID   10
#define _PIIX4_BRIDGE    0
#define _PIIX4_IDE       1
#define _PIIX4_USB       2
#define _PIIX4_POWER     3

#define CYG_PCI_CFG_PIIX4_PIRQR          0x60
#define CYG_PCI_CFG_PIIX4_SERIRQC        0x64
#define CYG_PCI_CFG_PIIX4_TOM            0x69
#define CYG_PCI_CFG_PIIX4_GENCFG         0xb0

#define CYG_PCI_CFG_PIIX4_IDETIM         0x40
#define CYG_PCI_CFG_PIIX4_IDETIM_IDE     0x8000
#define CYG_PCI_CFG_PIIX4_IDETIM_SITRE   0x4000
#define CYG_PCI_CFG_PIIX4_IDETIM_DTE1    0x0080
#define CYG_PCI_CFG_PIIX4_IDETIM_PPE1    0x0040
#define CYG_PCI_CFG_PIIX4_IDETIM_IE1     0x0020
#define CYG_PCI_CFG_PIIX4_IDETIM_TIME1   0x0010
#define CYG_PCI_CFG_PIIX4_IDETIM_DTE0    0x0008
#define CYG_PCI_CFG_PIIX4_IDETIM_PPE0    0x0004
#define CYG_PCI_CFG_PIIX4_IDETIM_IE0     0x0002
#define CYG_PCI_CFG_PIIX4_IDETIM_TIME0   0x0001

#define CYG_PCI_CFG_PIIX4_SERIRQC_ENABLE 0x80
#define CYG_PCI_CFG_PIIX4_SERIRQC_CONT   0x40

#define CYG_PCI_CFG_PIIX4_TOM_TOM_MASK 0xf0
#define CYG_PCI_CFG_PIIX4_TOM_TOM_16M  0xf0

#define CYG_PCI_CFG_PIIX4_GENCFG_ISA    0x00000001
#define CYG_PCI_CFG_PIIX4_GENCFG_SERIRQ 0x00010000



/* Malta Registers */
#define HAL_MALTA_REGISTER_BASE                 0xBF000000

#define HAL_MALTA_NMISTATUS_OFFSET              0x00000024
#define HAL_MALTA_NMIACK_OFFSET                 0x00000104
#define HAL_MALTA_SOFTRES_OFFSET                0x00000500
#define HAL_MALTA_BRKRES_OFFSET                 0x00000508
#define HAL_MALTA_REVISION_OFFSET               0x00C00010

#define HAL_MALTA_NMISTATUS                     HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_NMISTATUS_OFFSET)
#define HAL_MALTA_NMIACK                        HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_NMIACK_OFFSET)
#define HAL_MALTA_SOFTRES                       HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_SOFTRES_OFFSET)
#define HAL_MALTA_BRKRES                        HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_BRKRES_OFFSET)
#define HAL_MALTA_REVISION                      HAL_REG(HAL_MALTA_REGISTER_BASE + HAL_MALTA_REVISION_OFFSET)

/* Malta NMI controller fields */
#define HAL_MALTA_NMISTATUS_FLAG                0x00000001
#define HAL_MALTA_NMIACK_FLAG                   0x00000001

/* Malta softreset fields */
#define HAL_MALTA_GORESET                       0x42

/* Malta brkreset fields */
#define HAL_MALTA_BRKRES_DEFAULT_VALUE          0xA

// PIIX4 registers
#define HAL_PIIX4_REGISTER_BASE        0xb8000000

// PIIX4 interrupt controller stuff
#define HAL_PIIX4_MASTER_ICW1          HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0020)
#define HAL_PIIX4_MASTER_ICW2          HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0021)
#define HAL_PIIX4_MASTER_ICW3          HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0021)
#define HAL_PIIX4_MASTER_ICW4          HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0021)
#define HAL_PIIX4_MASTER_OCW3          HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0020)
#define HAL_PIIX4_MASTER_OCW1          HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x0021)

#define HAL_PIIX4_SLAVE_ICW1           HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a0)
#define HAL_PIIX4_SLAVE_OCW3           HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a0)
#define HAL_PIIX4_SLAVE_ICW2           HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a1)
#define HAL_PIIX4_SLAVE_ICW3           HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a1)
#define HAL_PIIX4_SLAVE_ICW4           HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a1)
#define HAL_PIIX4_SLAVE_OCW1           HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x00a1)

#define HAL_PIIX4_MASTER_SLAVE_OFFSET  0x80

#define HAL_PIIX4_ELCR1                HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x04d0)
#define HAL_PIIX4_ELCR2                HAL_REG(HAL_PIIX4_REGISTER_BASE + 0x04d1)

#define HAL_PIIX4_ICW1_SEL             0x10
#define HAL_PIIX4_ICW1_WR              0x01
#define HAL_PIIX4_ICW3_CASCADE         0x04
#define HAL_PIIX4_ICW3_SLAVE           0x02
#define HAL_PIIX4_ICW4_UPMODE          0x01

#define HAL_PIIX4_OCW3_ESSM            0x40
#define HAL_PIIX4_OCW3_SEL             0x08
#define HAL_PIIX4_OCW3_REQ             0x02
#define HAL_PIIX4_OCW3_IS              0x03

#define HAL_PIIX4_ELCR1_MASK           0xf8
#define HAL_PIIX4_ELCR2_MASK           0xde

// PIIX4 IDE interface
#define HAL_PIIX4_IDE_PRI_CMD          (HAL_PIIX4_REGISTER_BASE + 0x01f0)
#define HAL_PIIX4_IDE_PRI_CTL          (HAL_PIIX4_REGISTER_BASE + 0x03f4)
#define HAL_PIIX4_IDE_SEC_CMD          (HAL_PIIX4_REGISTER_BASE + 0x0170)
#define HAL_PIIX4_IDE_SEC_CTL          (HAL_PIIX4_REGISTER_BASE + 0x0374)

/* Galileo Registers */
#define HAL_GALILEO_REGISTER_BASE               0xB4000000
#define HAL_GALILEO_PCI0_MEM0_BASE              0xB2000000

#define HAL_GALILEO_CPU_INTERFACE_CONFIG_OFFSET 0x0
#define HAL_GALILEO_INT_SPACE_DECODE_OFFSET     0x68
#define HAL_GALILEO_CS3_HIGH_DECODE_OFFSET      0x43c
#define HAL_GALILEO_CSBOOT_LOW_DECODE_OFFSET    0x440
#define HAL_GALILEO_CSBOOT_HIGH_DECODE_OFFSET   0x444

/* Galileo CPU Interface config fields */
#define HAL_GALILEO_BYTE_SWAP                   (BIT16 | BIT0)

#define HAL_GALILEO_CACHEOPMAP_MASK             0x000001FF
#define HAL_GALILEO_CACHEPRES_MASK              0x00000200
#define HAL_GALILEO_WRITEMODE_MASK              0x00000800
#define HAL_GALILEO_ENDIAN_MASK                 0x00001000
#define HAL_GALILEO_R5KL2_MASK                  0x00004000
#define HAL_GALILEO_EXT_HIT_DELAY_MASK          0x00008000
#define HAL_GALILEO_CPU_WRITERATE_MASK          0x00010000
#define HAL_GALILEO_STOP_RETRY_MASK             0x00020000
#define HAL_GALILEO_MULTI_GT_MASK               0x00040000
#define HAL_GALILEO_SYSADCVALID_MASK            0x00080000