📄 plf_intr.h
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#define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
#endif
//--------------------------------------------------------------------------
// Interrupt controler information
// V320USC
#define CYGARC_REG_INT_STAT 0xb80000ec
#define CYGARC_REG_INT_CFG0 0xb80000e0
#define CYGARC_REG_INT_CFG1 0xb80000e4
#define CYGARC_REG_INT_CFG2 0xb80000e8
#define CYGARC_REG_INT_CFG3 0xb8000158
#define CYGARC_REG_INT_CFG_INT0 0x00000100
#define CYGARC_REG_INT_CFG_INT1 0x00000200
#define CYGARC_REG_INT_CFG_INT2 0x00000400
#define CYGARC_REG_INT_CFG_INT3 0x00000800
// FPGA
#define CYGARC_REG_PCI_STAT 0xb5300000
#define CYGARC_REG_PCI_MASK 0xb5300030
#define CYGARC_REG_IO_STAT 0xb5300010
#define CYGARC_REG_IO_MASK 0xb5300040
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \
HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
_mask_ &= ~(1<<_shift_); \
HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
} \
else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \
HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
_mask_ &= ~(1<<_shift_); \
HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
} else { /* V320USC */ \
cyg_uint32 _mask_; \
cyg_uint32 _shift_ = \
(_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
_mask_ &= !(1<<_shift_); \
HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
} \
CYG_MACRO_END
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
if( (_vector_) <= CYGNUM_HAL_INTERRUPT_COMPARE ) \
{ \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"or $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
} \
else if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_IO_base; \
HAL_READ_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
_mask_ |= (1<<_shift_); \
HAL_WRITE_UINT8(CYGARC_REG_IO_MASK, _mask_ ); \
} \
else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) \
{ \
cyg_uint8 _mask_; \
cyg_uint32 _shift_ = (_vector_)-CYGNUM_HAL_INTERRUPT_INTC_PCI_base; \
HAL_READ_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
_mask_ |= (1<<_shift_); \
HAL_WRITE_UINT8(CYGARC_REG_PCI_MASK, _mask_ ); \
} else { /* V320USC */ \
cyg_uint32 _mask_; \
cyg_uint32 _shift_ = \
(_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
HAL_READ_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
_mask_ |= (1<<_shift_); \
HAL_WRITE_UINT32(CYGARC_REG_INT_CFG0, _mask_ ); \
} \
CYG_MACRO_END
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
cyg_uint32 _srvector_ = _vector_; \
if ((_vector_) >= CYGNUM_HAL_INTERRUPT_INTC_IO_base) { \
_srvector_ = CYGNUM_HAL_INTERRUPT_IO; \
} else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_PCI_base) { \
_srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT1; \
} else if (_vector_ >= CYGNUM_HAL_INTERRUPT_INTC_V320USC_base) { \
cyg_uint32 _mask_; \
cyg_uint32 _shift_ = \
(_vector_)-CYGNUM_HAL_INTERRUPT_INTC_V320USC_base; \
_mask_ = (1<<_shift_); \
HAL_WRITE_UINT32(CYGARC_REG_INT_STAT, _mask_ ); \
_srvector_ = CYGNUM_HAL_INTERRUPT_V320USC_INT0; \
} \
asm volatile ( \
"mfc0 $3,$13\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$13\n" \
"nop; nop; nop\n" \
: \
: "r"(_srvector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
//----------------------------------------------------------------------------
// Reset.
#define CYGARC_REG_BOARD_RESET 0xb5400000
#define HAL_PLATFORM_RESET() HAL_WRITE_UINT8(CYGARC_REG_BOARD_RESET,0)
#define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_PLF_INTR_H
// End of plf_intr.h
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