platform.s

开放源码实时操作系统源码.

	nop
	b	8f
	li	v1, 0
0:
	ori	s5, HAL_GALILEO_SDRAM_BANK0_PARITY
	li	v1, 1
8:

	#
	# Setup number of device banks
	# Only support 2 or 4 banks
	#
	li	t0, 2
	beq	s2, t0, 8f
	nop
	li	t0, 4
	beq	s2, t0, 0f
	nop
	b	error
	nop
0:
	ori	s5, HAL_GALILEO_SDRAM_NUM_BANKS_4
8:

	#
	# Now actually store the bank config register
	#
	sw	s5, HAL_GALILEO_SDRAM_BANK0_OFFSET(s7)
	sw	s5, HAL_GALILEO_SDRAM_BANK2_OFFSET(s7)

	#
	# Setup the SDRAM configuration register
	# All other fields are zero, and the proper value is masked
	# in when they are known
	#
	li	s5, HAL_GALILEO_SDRAM_DUPLICATE_BANK_ADDR | HAL_GALILEO_SDRAM_BANK_INTERLEAVE_DIS

	#
	# Setup the Refresh Rate
	#
	READ_SPD_VALUE HAL_SPD_GET_REFRESH_RATE, 0x7f, v0, NO_ERROR_CHECK

	li	t0, HAL_SPD_REFRESH_RATE_125
	beq	t0, v0, 8f
	li	t0, HAL_SPD_REFRESH_COUNTER_125

	li	t0, HAL_SPD_REFRESH_RATE_62_5
	beq	t0, v0, 8f
	li	t0, HAL_SPD_REFRESH_COUNTER_62_5

	li	t0, HAL_SPD_REFRESH_RATE_31_3
	beq	t0, v0, 8f
	li	t0, HAL_SPD_REFRESH_COUNTER_31_3

	li	t0, HAL_SPD_REFRESH_RATE_15_625
	beq	t0, v0, 8f
	li	t0, HAL_SPD_REFRESH_COUNTER_15_625

	li	t0, HAL_SPD_REFRESH_RATE_7_8
	beq	t0, v0, 8f
	li	t0, HAL_SPD_REFRESH_COUNTER_7_8

	# Unknown: assume 3.9 microseconds
	li	t0, HAL_SPD_REFRESH_COUNTER_3_9
8:

	or	s5, t0

	#
	# Setup RAM_WIDTH
	#
	beqz	v1, 8f
	nop
	READ_SPD_VALUE HAL_SPD_GET_ERROR_CHECK_WIDTH, 0x7f, v0, NO_ERROR_CHECK
	beq	v0, zero, 8f
	nop
	ori	s5, HAL_GALILEO_SDRAM_CFG_RAM_WIDTH
8:

	#
	# Store the SDRAM configuration register
	#
	sw	s5, HAL_GALILEO_SDRAM_CONFIG_OFFSET(s7)

	#
	# Reset SAA9730 now that we are done with the I2C unit.
	# This allows the generic PCI library to start with a clean
	# slate of devices on the PCI bus.
	#
	li	a0, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE)
	li	t0, HAL_SAA9730_SYSRESET_ALL
	sw	t0, HAL_SAA9730_SYSRESET_OFFSET(a0)
	
	#
	# Change the Galileo Base address to HAL_ATLAS_CONTROLLER_BASE
	#
	li	t0, HAL_ATLAS_CONTROLLER_BASE_ISD_CONFIG
	sw	t0, HAL_GALILEO_INT_SPACE_DECODE_OFFSET(s7)
	li	s7, CYGARC_UNCACHED_ADDRESS(HAL_ATLAS_CONTROLLER_BASE)

	#
	# Setup SDRAM Bank 0 Address Decoding
	#
	li	a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_RAM_BASE)		 # Physical bottom of Bank 0
	add	a1, s0, a0
	subu	a1, 1							 # Physical top of Bank 0

	srl	t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT			 # Setup SCS[1:0]
	srl	t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT			 #   First level decoding
	sw	t0, HAL_GALILEO_SCS10_LD_OFFSET(s7)			 #   (ie Processor Decode Region)
	sw	t1, HAL_GALILEO_SCS10_HD_OFFSET(s7)			 #

	srl	t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT			 # Setup SCS0
	srl	t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT			 #   Second level decoding
	sw	t0, HAL_GALILEO_SCS0_LD_OFFSET(s7)			 #   (ie Device Sub-decode Region)
	sw	t1, HAL_GALILEO_SCS0_HD_OFFSET(s7)			 #

	#
	# Setup SDRAM Bank 1 Address Decoding
	#
	add	a0, s0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_RAM_BASE)	 # Physical bottom of Bank 1
	add	a1, a0, s1
	subu	a1, 1							 # Physical top of Bank 1

	srl	t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT			 # Setup SCS[3:2]
	srl	t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT			 #   First level decoding
	sw	t0, HAL_GALILEO_SCS32_LD_OFFSET(s7)			 #   (ie Processor Decode Region)
	sw	t1, HAL_GALILEO_SCS32_HD_OFFSET(s7)			 #

	srl	t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT			 # Setup SCS2
	srl	t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT			 #   Second level decoding
	sw	t0, HAL_GALILEO_SCS2_LD_OFFSET(s7)			 #   (ie Device Sub-decode Region)
	sw	t1, HAL_GALILEO_SCS2_HD_OFFSET(s7)			 #

	#
	# Setup PCI windows
	#
	li	a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_MEM0_BASE)
	add	a1, a0, HAL_ATLAS_PCI_MEM0_SIZE
	subu	a1, 1							 # Physical top of Bank 1
	srl	t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT
	srl	t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT
	sw	t0, HAL_GALILEO_PCIMEM0_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_PCIMEM0_HD_OFFSET(s7)
	
	li	a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_MEM1_BASE)
	add	a1, a0, HAL_ATLAS_PCI_MEM1_SIZE
	subu	a1, 1							 # Physical top of Bank 1
	srl	t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT
	srl	t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT
	sw	t0, HAL_GALILEO_PCIMEM1_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_PCIMEM1_HD_OFFSET(s7)

	li	a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_PCI_IO_BASE)
	add	a1, a0, HAL_ATLAS_PCI_IO_SIZE
	subu	a1, 1							 # Physical top of Bank 1
	srl	t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT
	srl	t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT
	sw	t0, HAL_GALILEO_PCIIO_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_PCIIO_HD_OFFSET(s7)

	#
	# Setup FLASH Address Decoding
	#
	li	a0, CYGARC_PHYSICAL_ADDRESS(HAL_ATLAS_FLASH_BASE)	 # Physical bottom of Flash Bank
	add	a1, a0, HAL_ATLAS_FLASH_SIZE
	subu	a1, 1							 # Physical top of Flash Bank

	srl	t0, a0, HAL_GALILEO_CPU_DECODE_SHIFT			 # Setup CS[2:0]
	srl	t1, a1, HAL_GALILEO_CPU_DECODE_SHIFT			 #   First level decoding
	sw	t0, HAL_GALILEO_CS20_LD_OFFSET(s7)			 #   (ie Processor Decode Region)
	sw	t1, HAL_GALILEO_CS20_HD_OFFSET(s7)			 #

	srl	t0, a0, HAL_GALILEO_DEV_DECODE_SHIFT			 # Setup CS0
	srl	t1, a1, HAL_GALILEO_DEV_DECODE_SHIFT			 #   Second level decoding
	sw	t0, HAL_GALILEO_CS0_LD_OFFSET(s7)			 #   (ie Device Sub-decode Region)
	sw	t1, HAL_GALILEO_CS0_HD_OFFSET(s7)			 #

	#
	#  Now disable all unused decodes
	#  (SCS1, SCS3, PCI1xx, CS1, CS2)
	#
	li	t0, 0xffff
	move	t1, zero
	sw	t0, HAL_GALILEO_SCS1_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_SCS1_HD_OFFSET(s7)
	sw	t0, HAL_GALILEO_SCS3_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_SCS3_HD_OFFSET(s7)
	sw	t0, HAL_GALILEO_PCI1IO_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_PCI1IO_HD_OFFSET(s7)
	sw	t0, HAL_GALILEO_PCI1MEM0_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_PCI1MEM0_HD_OFFSET(s7)
	sw	t0, HAL_GALILEO_PCI1MEM1_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_PCI1MEM1_HD_OFFSET(s7)
	sw	t0, HAL_GALILEO_CS1_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_CS1_HD_OFFSET(s7)
	sw	t0, HAL_GALILEO_CS2_LD_OFFSET(s7)
	sw	t1, HAL_GALILEO_CS2_HD_OFFSET(s7)

noerror:
	move	v0, zero
	add	v1, s0, s1
	move	ra, s8
	jr	ra
	nop

error:
	li	v0, HAL_ATLAS_MEMERROR
	move	ra, s8
	jr	ra
	nop

FUNC_END(hal_atlas_init_sdram)

##
## Read a value from the SDRAM SPD device.
##
## Parameters:	 a0 = subaddress
## Returns:	 v0 = SPD value read
##
FUNC_START(read_spd_value)
	#
	# Setup a base address register
	#
	li	a1, CYGARC_UNCACHED_ADDRESS(HAL_GALILEO_PCI0_MEM0_BASE)

	#
	# Write the I2C command
	#
	sll	a0, 16
	li	t0, (HAL_SAA9730_I2CTFR_ATTR1_CONT | \
		     ((0xa0 << 24) | HAL_SAA9730_I2CTFR_ATTR2_START) | \
		     ((0xa1 << 8) | HAL_SAA9730_I2CTFR_ATTR0_START))
	or	a0, t0
	sw	a0, HAL_SAA9730_I2CTFR_OFFSET(a1)
1:	lw	t0, HAL_SAA9730_I2CTFR_OFFSET(a1)
	and	t0, 0x1
	bnez	t0, 1b
	nop

	#
	# Read the SPD value
	#
	li	a0, HAL_SAA9730_I2CTFR_ATTR2_STOP
	sw	a0, HAL_SAA9730_I2CTFR_OFFSET(a1)
1:	lw	t0, HAL_SAA9730_I2CTFR_OFFSET(a1)
	and	t0, 0x1
	bnez	t0, 1b
	nop

	#
	# Setup the return value.
	#
	lw	v0, HAL_SAA9730_I2CTFR_OFFSET(a1)
	srl	v0, 24

	jr	ra
	nop
FUNC_END(read_spd_value)
#endif /* defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM) */

##-----------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.

	.extern hal_default_isr
	
	.data

	.globl	hal_interrupt_handlers
hal_interrupt_handlers:
	.rept	25
	.long	hal_default_isr
	.endr

	.globl	hal_interrupt_data
hal_interrupt_data:
	.rept	25
	.long	0
	.endr

	.globl	hal_interrupt_objects
hal_interrupt_objects:
	.rept	25
	.long	0
	.endr

	
##-----------------------------------------------------------------------------
## end of platform.S