📄 plf_io.h
字号:
# define HAL_GALILEO_IRQCAUSE_SLVRD (1 << 15)
# define HAL_GALILEO_IRQCAUSE_AERR (1 << 16)
# define HAL_GALILEO_IRQCAUSE_MERR (1 << 17)
# define HAL_GALILEO_IRQCAUSE_MASABT (1 << 18)
# define HAL_GALILEO_IRQCAUSE_TARABT (1 << 19)
# define HAL_GALILEO_IRQCAUSE_RETRY (1 << 20)
# define HAL_GALILEO_IRQCAUSE_CPUSUM (1 << 30)
# define HAL_GALILEO_IRQCAUSE_PCISUM (1 << 31)
#define HAL_GALILEO_HIRQ_CAUSE_OFFSET 0xc98
#define HAL_GALILEO_CPUIRQ_MASK_OFFSET 0xc1c
#define HAL_GALILEO_CPUHIRQ_MASK_OFFSET 0xc9c
#define HAL_SAA9730_I2CSC_I2CCC_6400 0x500
#define HAL_SAA9730_I2CTFR_ATTR0_START 0xC
#define HAL_SAA9730_I2CTFR_ATTR2_START 0xC0
#define HAL_SAA9730_I2CTFR_ATTR2_STOP 0x40
#define HAL_SAA9730_I2CTFR_ATTR1_CONT 0x20
#define HAL_SAA9730_I2CTFR_OFFSET 0x2400
#define HAL_SAA9730_I2CSC_OFFSET 0x2404
#define HAL_SAA9730_SYSRESET_OFFSET 0x4020
#define HAL_SAA9730_SYSRESET_ALL 0xdeae
#define HAL_SPD_GET_NUM_ROW_BITS 3
#define HAL_SPD_GET_NUM_COL_BITS 4
#define HAL_SPD_GET_NUM_MODULE_BANKS 5
#define HAL_SPD_GET_CONFIG_TYPE 11
#define HAL_SPD_GET_REFRESH_RATE 12
#define HAL_SPD_GET_SDRAM_WIDTH 13
#define HAL_SPD_GET_ERROR_CHECK_WIDTH 14
#define HAL_SPD_GET_BURST_LENGTH 16
#define HAL_SPD_GET_NUM_DEVICE_BANKS 17
#define HAL_SPD_GET_CAS_LAT 18
#define HAL_SPD_GET_ROW_DENSITY 31
#define HAL_SPD_CONFIG_TYPE_PARITY BIT0
#define HAL_SPD_CONFIG_TYPE_ECC BIT1
#define HAL_SPD_REFRESH_RATE_125 5
#define HAL_SPD_REFRESH_RATE_62_5 4
#define HAL_SPD_REFRESH_RATE_31_3 3
#define HAL_SPD_REFRESH_RATE_15_625 0
#define HAL_SPD_REFRESH_RATE_7_8 2
#define HAL_SPD_REFRESH_RATE_3_9 1
#define HAL_SPD_REFRESH_COUNTER_125 (125*2)
#define HAL_SPD_REFRESH_COUNTER_62_5 (62*2)
#define HAL_SPD_REFRESH_COUNTER_31_3 (31*2)
#define HAL_SPD_REFRESH_COUNTER_15_625 (15*2)
#define HAL_SPD_REFRESH_COUNTER_7_8 (7*2)
#define HAL_SPD_REFRESH_COUNTER_3_9 (3*2)
/* Atlas Display Registers */
#define HAL_DISPLAY_BASE (HAL_ATLAS_REGISTER_BASE + 0x400)
#define HAL_DISPLAY_LEDGREEN_OFFSET 0x00
#define HAL_DISPLAY_LEDBAR_OFFSET 0x08
#define HAL_DISPLAY_ASCIIWORD_OFFSET 0x10
#define HAL_DISPLAY_ASCIIPOS0_OFFSET 0x18
#define HAL_DISPLAY_ASCIIPOS1_OFFSET 0x20
#define HAL_DISPLAY_ASCIIPOS2_OFFSET 0x28
#define HAL_DISPLAY_ASCIIPOS3_OFFSET 0x30
#define HAL_DISPLAY_ASCIIPOS4_OFFSET 0x38
#define HAL_DISPLAY_ASCIIPOS5_OFFSET 0x40
#define HAL_DISPLAY_ASCIIPOS6_OFFSET 0x48
#define HAL_DISPLAY_ASCIIPOS7_OFFSET 0x50
#define HAL_DISPLAY_LEDGREEN HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDGREEN_OFFSET)
#define HAL_DISPLAY_LEDBAR HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_LEDBAR_OFFSET)
#define HAL_DISPLAY_ASCIIWORD HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIWORD_OFFSET)
#define HAL_DISPLAY_ASCIIPOS0 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS0_OFFSET)
#define HAL_DISPLAY_ASCIIPOS1 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS1_OFFSET)
#define HAL_DISPLAY_ASCIIPOS2 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS2_OFFSET)
#define HAL_DISPLAY_ASCIIPOS3 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS3_OFFSET)
#define HAL_DISPLAY_ASCIIPOS4 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS4_OFFSET)
#define HAL_DISPLAY_ASCIIPOS5 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS5_OFFSET)
#define HAL_DISPLAY_ASCIIPOS6 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS6_OFFSET)
#define HAL_DISPLAY_ASCIIPOS7 HAL_REG(HAL_DISPLAY_BASE + HAL_DISPLAY_ASCIIPOS7_OFFSET)
#ifdef __ASSEMBLER__
# define DEBUG_ASCII_DISPLAY(register, character) \
li k0, CYGARC_UNCACHED_ADDRESS(register); \
li k1, character; \
sw k1, 0(k0); \
nop; \
nop; \
nop
# define DEBUG_LED_IMM(val) \
li k0, HAL_DISPLAY_LEDBAR; \
li k1, val; \
sw k1, 0(k0)
# define DEBUG_LED_REG(reg) \
li k0, HAL_DISPLAY_LEDBAR; \
sw reg, 0(k0)
# define DEBUG_HEX_DISPLAY_IMM(val) \
li k0, HAL_DISPLAY_ASCIIWORD; \
li k1, val; \
sw k1, 0(k0)
# define DEBUG_HEX_DISPLAY_REG(reg) \
li k0, HAL_DISPLAY_ASCIIWORD; \
sw reg, 0(k0)
# define DEBUG_DELAY() \
li k0, 0x20000; \
0: sub k0, k0, 1; \
bnez k0, 0b; \
nop
#else
# define DEBUG_ASCII_DISPLAY(register, character) \
*(register) = character
# define DEBUG_LED_IMM(val) \
*HAL_DISPLAY_LEDBAR = val
# define DEBUG_HEX_DISPLAY_IMM(val) \
*HAL_DISPLAY_ASCIIWORD = val
# define DEBUG_DELAY() \
{ \
volatile int i = 0x20000; \
while (--i) ; \
}
# define DEBUG_DISPLAY(str) \
{ \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS0, str[0]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS1, str[1]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS2, str[2]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS3, str[3]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS4, str[4]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS5, str[5]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS6, str[6]); \
DEBUG_ASCII_DISPLAY(HAL_DISPLAY_ASCIIPOS7, str[7]); \
}
#define HAL_GALILEO_PUTREG(x,y) \
(*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_ATLAS_CONTROLLER_BASE) + (x))) = (y))
#define HAL_GALILEO_GETREG(x) \
(*((volatile unsigned *)(CYGARC_UNCACHED_ADDRESS(HAL_ATLAS_CONTROLLER_BASE) + (x))))
extern cyg_uint32 cyg_hal_plf_pci_cfg_read_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern cyg_uint16 cyg_hal_plf_pci_cfg_read_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern cyg_uint8 cyg_hal_plf_pci_cfg_read_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset);
extern void cyg_hal_plf_pci_cfg_write_dword (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint32 val);
extern void cyg_hal_plf_pci_cfg_write_word (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint16 val);
extern void cyg_hal_plf_pci_cfg_write_byte (cyg_uint32 bus,
cyg_uint32 devfn,
cyg_uint32 offset,
cyg_uint8 val);
// Initialize the PCI bus.
externC void cyg_hal_plf_pci_init(void);
#define HAL_PCI_INIT() cyg_hal_plf_pci_init()
// Map PCI device resources starting from these addresses in PCI space.
#define HAL_PCI_ALLOC_BASE_MEMORY 0x08000000
#define HAL_PCI_ALLOC_BASE_IO 0x18000000
// This is where the PCI spaces are mapped in the CPU's address space.
//
#define HAL_PCI_PHYSICAL_MEMORY_BASE 0xA0000000
#define HAL_PCI_PHYSICAL_IO_BASE 0xA0000000
// Read a value from the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_byte((__bus), (__devfn), (__offset))
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_word((__bus), (__devfn), (__offset))
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
__val = cyg_hal_plf_pci_cfg_read_dword((__bus), (__devfn), (__offset))
// Write a value to the PCI configuration space of the appropriate
// size at an address composed from the bus, devfn and offset.
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_byte((__bus), (__devfn), (__offset), (__val))
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_word((__bus), (__devfn), (__offset), (__val))
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
cyg_hal_plf_pci_cfg_write_dword((__bus), (__devfn), (__offset), (__val))
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
CYG_MACRO_START \
cyg_uint8 __req; \
HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
if (0 != __req) { \
CYG_ADDRWORD __translation[4] = { \
CYGNUM_HAL_INTERRUPT_INTA, \
CYGNUM_HAL_INTERRUPT_INTB, \
CYGNUM_HAL_INTERRUPT_INTC, \
CYGNUM_HAL_INTERRUPT_INTD}; \
\
/* The PCI #INT lines for different device numbers are wired like this: */ \
/* */ \
/* Int. Ctrl. PCI_A PCI_B PCI_C PCI_D */ \
/* Device no. */ \
/* 0, 4, ..28 INTC# INTD# INTA# INTB# */ \
/* 1, 5, ..29 INTD# INTA# INTB# INTC# */ \
/* 2, 6, ..30 INTA# INTB# INTC# INTD# */ \
/* 3, 7, ..31 INTB# INTC# INTD# INTA# */ \
\
__vec = __translation[(((__req+1)+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
__valid = true; \
} else { \
/* Device will not generate interrupt requests. */ \
__valid = false; \
} \
CYG_MACRO_END
// Galileo GT64120 on MIPS ATLAS requires special processing.
// First, it will hang when accessing device 31 on the local bus.
// Second, we need to ignore the GT64120 so we can set it up
// outside the generic PCI library.
#define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn) \
((__bus) == 0 && ((__dev) == 0 || (__dev) == 31))
#endif
//-----------------------------------------------------------------------------
// end of plf_io.h
#endif // CYGONCE_PLF_IO_H
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -