📄 hal_arch.h
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#define HAL_SET_GDB_FPU_REGISTERS( _regs_ , _regval_ )
#endif
// Some targets also report the state of all the coprocessor 0
// registers to GDB. If that is the case then
// CYGPKG_HAL_MIPS_GDB_REPORT_CP0 will be defined and the
// HAL_[G|S]ET_CP0_REGISTER_*() macros will be defined.
#ifdef CYGPKG_HAL_MIPS_GDB_REPORT_CP0
#define HAL_GET_GDB_CP0_REGISTERS( _regval_, _regs_ ) \
HAL_GET_CP0_REGISTER_32( _regval_[74], 0, 0 ); /* index */ \
HAL_GET_CP0_REGISTER_32( _regval_[75], 1, 0 ); /* random */ \
HAL_GET_CP0_REGISTER_32( _regval_[76], 2, 0 ); /* EntryLo0 */ \
HAL_GET_CP0_REGISTER_32( _regval_[77], 3, 0 ); /* EntryLo1 */ \
HAL_GET_CP0_REGISTER_64( _regval_[78], 4, 0 ); /* context */ \
HAL_GET_CP0_REGISTER_32( _regval_[79], 5, 0 ); /* PageMask */ \
HAL_GET_CP0_REGISTER_32( _regval_[80], 6, 0 ); /* Wired */ \
(_regval_)[81] = 0xC0C0C006; \
(_regval_)[82] = (_regs_)->badvr; /* BadVr */ \
HAL_GET_CP0_REGISTER_32( _regval_[83], 9, 0 ); /* Count */ \
HAL_GET_CP0_REGISTER_64( _regval_[84], 10, 0 ); /* EntryHi */ \
HAL_GET_CP0_REGISTER_32( _regval_[85], 11, 0 ); /* Compare */ \
(_regval_)[86] = (_regs_)->sr; /* Status */ \
(_regval_)[87] = (_regs_)->cause; /* Cause */ \
HAL_GET_CP0_REGISTER_64( _regval_[88], 14, 0 ); /* EPC */ \
HAL_GET_CP0_REGISTER_32( _regval_[89], 15, 0 ); /* PRId */ \
HAL_GET_CP0_REGISTER_32( _regval_[90], 16, 0 ); /* Config */ \
HAL_GET_CP0_REGISTER_32( _regval_[91], 17, 0 ); /* LLAddr */ \
HAL_GET_CP0_REGISTER_64( _regval_[92], 18, 0 ); /* WatchLo */ \
HAL_GET_CP0_REGISTER_32( _regval_[93], 19, 0 ); /* WatchHi */ \
HAL_GET_CP0_REGISTER_64( _regval_[94], 20, 0 ); /* XContext */ \
(_regval_)[95] = 0xC0C0C021; \
(_regval_)[96] = 0xC0C0C022; \
HAL_GET_CP0_REGISTER_32( _regval_[97], 23, 0 ); /* Debug */ \
HAL_GET_CP0_REGISTER_64( _regval_[98], 24, 0 ); /* DEPC */ \
(_regval_)[99] = 0xC0C0C025; \
HAL_GET_CP0_REGISTER_32( _regval_[100], 26, 0 ); /* ErrCtl */ \
HAL_GET_CP0_REGISTER_32( _regval_[101], 27, 0 ); /* CacheErr */ \
HAL_GET_CP0_REGISTER_32( _regval_[102], 28, 0 ); /* TagLo */ \
HAL_GET_CP0_REGISTER_32( _regval_[103], 29, 0 ); /* TagHi */ \
HAL_GET_CP0_REGISTER_64( _regval_[104], 30, 0 ); /* ErrorEPC */ \
HAL_GET_CP0_REGISTER_64( _regval_[105], 31, 0 ); /* DESAVE */ \
HAL_GET_CP0_REGISTER_32( _regval_[106], 16, 1 ); /* Config1 */
#define HAL_SET_GDB_CP0_REGISTERS( _regval_, _regs_ ) \
HAL_SET_CP0_REGISTER_32( _regval_[74], 0, 0 ); /* index */ \
HAL_SET_CP0_REGISTER_32( _regval_[76], 2, 0 ); /* EntryLo0 */ \
HAL_SET_CP0_REGISTER_32( _regval_[77], 3, 0 ); /* EntryLo1 */ \
HAL_SET_CP0_REGISTER_64( _regval_[78], 4, 0 ); /* context */ \
HAL_SET_CP0_REGISTER_32( _regval_[79], 5, 0 ); /* PageMask */ \
HAL_SET_CP0_REGISTER_32( _regval_[80], 6, 0 ); /* Wired */ \
HAL_SET_CP0_REGISTER_32( _regval_[83], 9, 0 ); /* Count */ \
HAL_SET_CP0_REGISTER_64( _regval_[84], 10, 0 ); /* EntryHi */ \
HAL_SET_CP0_REGISTER_32( _regval_[85], 11, 0 ); /* Compare */ \
HAL_SET_CP0_REGISTER_32( _regval_[90], 16, 0 ); /* Config */ \
HAL_SET_CP0_REGISTER_64( _regval_[92], 18, 0 ); /* WatchLo */ \
HAL_SET_CP0_REGISTER_32( _regval_[93], 19, 0 ); /* WatchHi */ \
HAL_SET_CP0_REGISTER_64( _regval_[94], 20, 0 ); /* XContext */ \
HAL_SET_CP0_REGISTER_32( _regval_[97], 23, 0 ); /* Debug */ \
HAL_SET_CP0_REGISTER_64( _regval_[98], 24, 0 ); /* DEPC */ \
HAL_SET_CP0_REGISTER_32( _regval_[100], 26, 0 ); /* ErrCtl */ \
HAL_SET_CP0_REGISTER_32( _regval_[101], 27, 0 ); /* CacheErr */ \
HAL_SET_CP0_REGISTER_32( _regval_[102], 28, 0 ); /* TagLo */ \
HAL_SET_CP0_REGISTER_32( _regval_[103], 29, 0 ); /* TagHi */ \
HAL_SET_CP0_REGISTER_64( _regval_[105], 31, 0 ); /* DESAVE */
#else
#define HAL_GET_GDB_CP0_REGISTERS( _regval_, _regs_ )
#define HAL_SET_GDB_CP0_REGISTERS( _regval_, _regs_ )
#endif
// Copy a set of registers from a HAL_SavedRegisters structure into a
// GDB ordered array.
#define HAL_GET_GDB_REGISTERS( _aregval_ , _regs_ ) \
{ \
CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < 32; _i_++ ) \
_regval_[_i_] = (_regs_)->d[_i_]; \
\
HAL_GET_GDB_FPU_REGISTERS( _regval_, _regs_ ); \
\
_regval_[32] = (_regs_)->sr; \
_regval_[33] = (_regs_)->lo; \
_regval_[34] = (_regs_)->hi; \
_regval_[35] = (_regs_)->badvr; \
_regval_[36] = (_regs_)->cause; \
_regval_[37] = (_regs_)->pc; \
\
HAL_GET_GDB_CP0_REGISTERS( _regval_, _regs_ ); \
}
// Copy a GDB ordered array into a HAL_SavedRegisters structure.
#define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
{ \
CYG_HAL_GDB_REG *_regval_ = (CYG_HAL_GDB_REG *)(_aregval_); \
int _i_; \
\
for( _i_ = 0; _i_ < 32; _i_++ ) \
(_regs_)->d[_i_] = _regval_[_i_]; \
\
HAL_SET_GDB_FPU_REGISTERS( _regs_, _regval_ ); \
\
(_regs_)->sr = _regval_[32]; \
(_regs_)->lo = _regval_[33]; \
(_regs_)->hi = _regval_[34]; \
(_regs_)->badvr = _regval_[35]; \
(_regs_)->cause = _regval_[36]; \
(_regs_)->pc = _regval_[37]; \
\
HAL_SET_GDB_CP0_REGISTERS( _regval_, _regs_ ); \
}
//--------------------------------------------------------------------------
// HAL setjmp
// Note: These definitions are repeated in hal_arch.h. If changes are
// required remember to update both sets.
#define CYGARC_JMP_BUF_SP 0
#define CYGARC_JMP_BUF_R16 1
#define CYGARC_JMP_BUF_R17 2
#define CYGARC_JMP_BUF_R18 3
#define CYGARC_JMP_BUF_R19 4
#define CYGARC_JMP_BUF_R20 5
#define CYGARC_JMP_BUF_R21 6
#define CYGARC_JMP_BUF_R22 7
#define CYGARC_JMP_BUF_R23 8
#define CYGARC_JMP_BUF_R28 9
#define CYGARC_JMP_BUF_R30 10
#define CYGARC_JMP_BUF_R31 11
#define CYGARC_JMP_BUF_SIZE 12
typedef cyg_uint32 hal_jmp_buf[CYGARC_JMP_BUF_SIZE];
externC int hal_setjmp(hal_jmp_buf env);
externC void hal_longjmp(hal_jmp_buf env, int val);
//-------------------------------------------------------------------------
// Idle thread code.
// This macro is called in the idle thread loop, and gives the HAL the
// chance to insert code. Typical idle thread behaviour might be to halt the
// processor.
externC void hal_idle_thread_action(cyg_uint32 loop_count);
#define HAL_IDLE_THREAD_ACTION(_count_) hal_idle_thread_action(_count_)
//--------------------------------------------------------------------------
// Minimal and sensible stack sizes: the intention is that applications
// will use these to provide a stack size in the first instance prior to
// proper analysis. Idle thread stack should be this big.
// THESE ARE NOT INTENDED TO BE MICROMETRICALLY ACCURATE FIGURES.
// THEY ARE HOWEVER ENOUGH TO START PROGRAMMING.
// YOU MUST MAKE YOUR STACKS LARGER IF YOU HAVE LARGE "AUTO" VARIABLES!
// This is not a config option because it should not be adjusted except
// under "enough rope" sort of disclaimers.
// Typical case stack frame size: return link + 4 pushed registers + some locals.
#define CYGNUM_HAL_STACK_FRAME_SIZE (48)
// Stack needed for a context switch:
#if defined(CYGHWR_HAL_MIPS_FPU)
# if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
#define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*CYG_HAL_MIPS_REG_SIZE)+(32*8))
# elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
#define CYGNUM_HAL_STACK_CONTEXT_SIZE (((32+12)*CYG_HAL_MIPS_REG_SIZE)+(32*4))
# else
# error MIPS FPU register size not defined
# endif
#else
#define CYGNUM_HAL_STACK_CONTEXT_SIZE ((32+10)*CYG_HAL_MIPS_REG_SIZE)
#endif
// Interrupt + call to ISR, interrupt_end() and the DSR
#define CYGNUM_HAL_STACK_INTERRUPT_SIZE (4+2*CYGNUM_HAL_STACK_CONTEXT_SIZE)
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
// An interrupt stack which is large enough for all possible interrupt
// conditions (and only used for that purpose) exists. "User" stacks
// can be much smaller
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (CYGNUM_HAL_STACK_CONTEXT_SIZE+ \
CYGNUM_HAL_STACK_INTERRUPT_SIZE*2+ \
CYGNUM_HAL_STACK_FRAME_SIZE*8)
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (CYGNUM_HAL_STACK_SIZE_MINIMUM+1024)
#else // CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
// No separate interrupt stack exists. Make sure all threads contain
// a stack sufficiently large.
#define CYGNUM_HAL_STACK_SIZE_MINIMUM (4096)
#define CYGNUM_HAL_STACK_SIZE_TYPICAL (4096)
#endif
#endif /* __ASSEMBLER__ */
// Convenience macros for accessing memory cached or uncached
#define CYGARC_KSEG_MASK (0xE0000000)
#define CYGARC_KSEG_CACHED (0x80000000)
#define CYGARC_KSEG_UNCACHED (0xA0000000)
#define CYGARC_KSEG_CACHED_BASE (0x80000000)
#define CYGARC_KSEG_UNCACHED_BASE (0xA0000000)
#ifndef __ASSEMBLER__
#define CYGARC_CACHED_ADDRESS(x) ((((CYG_ADDRESS)(x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_CACHED)
#define CYGARC_UNCACHED_ADDRESS(x) ((((CYG_ADDRESS)(x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_UNCACHED)
#define CYGARC_PHYSICAL_ADDRESS(x) (((CYG_ADDRESS)(x)) & ~CYGARC_KSEG_MASK)
#else // __ASSEMBLER__
#define CYGARC_CACHED_ADDRESS(x) ((((x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_CACHED)
#define CYGARC_UNCACHED_ADDRESS(x) ((((x)) & ~CYGARC_KSEG_MASK) | CYGARC_KSEG_UNCACHED)
#define CYGARC_PHYSICAL_ADDRESS(x) (((x)) & ~CYGARC_KSEG_MASK)
#define CYGARC_ADDRESS_REG_CACHED(reg) \
and reg, reg, ~CYGARC_KSEG_MASK; \
or reg, reg, CYGARC_KSEG_CACHED
#define CYGARC_ADDRESS_REG_UNCACHED(reg) \
and reg, reg, ~CYGARC_KSEG_MASK; \
or reg, reg, CYGARC_KSEG_UNCACHED
#endif /* __ASSEMBLER__ */
//--------------------------------------------------------------------------
// Macros for switching context between two eCos instances (jump from
// code in ROM to code in RAM or vice versa).
#define CYGARC_HAL_SAVE_GP() \
CYG_MACRO_START \
register CYG_ADDRWORD __gp_save; \
asm volatile ( "move %0,$28;" \
".extern _gp;" \
"la $gp,_gp;" \
: "=r"(__gp_save))
#define CYGARC_HAL_RESTORE_GP() \
asm volatile ( "move $gp,%0;" :: "r"(__gp_save) ); \
CYG_MACRO_END
//--------------------------------------------------------------------------
// Macro for finding return address.
#define CYGARC_HAL_GET_RETURN_ADDRESS(_x_, _dummy_) \
asm volatile ( "move %0,$31;" : "=r" (_x_) )
#define CYGARC_HAL_GET_RETURN_ADDRESS_BACKUP(_dummy_)
//--------------------------------------------------------------------------
#endif // CYGONCE_HAL_HAL_ARCH_H
// End of hal_arch.h
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