arch.inc

开放源码实时操作系统源码.

# Register save and restore macros. These expect a pointer to a CPU save state
# area in the register \ptr. The GPR indicated by \reg will be saved into its
# slot in that structure.

#ifdef CYGHWR_HAL_MIPS_64BIT

	.macro sgpr reg,ptr
	sd	$\reg,(mipsreg_regs+\reg*mips_regsize)(\ptr)
	.endm

	.macro lgpr reg,ptr
	ld	$\reg,(mipsreg_regs+\reg*mips_regsize)(\ptr)
	.endm

	.macro slo reg,ptr
	sd	\reg,(mipsreg_lo)(\ptr)
	.endm

	.macro shi reg,ptr
	sd	\reg,(mipsreg_hi)(\ptr)
	.endm

	.macro llo reg,ptr
	ld	\reg,(mipsreg_lo)(\ptr)
	.endm

	.macro lhi reg,ptr
	ld	\reg,(mipsreg_hi)(\ptr)
	.endm

	.macro ssp reg,ptr
	sd	\reg,(mipsreg_regs+29*mips_regsize)(\ptr)
	.endm

	.macro lsp reg,ptr
	ld	\reg,(mipsreg_regs+29*mips_regsize)(\ptr)
	.endm

	.macro sva reg,val
	sd	\reg,\val
	.endm

	.macro lva reg,val
	ld	\reg,\val
	.endm

	.macro mvafc0 gpr,cpr
	dmfc0	\gpr,\cpr
	.endm

	.macro mvatc0 gpr,cpr
	dmtc0	\gpr,\cpr
	.endm

	.macro lpc reg,ptr
	ld	\reg,(mipsreg_pc)(\ptr)
	.endm

	.macro spc reg,ptr
	sd	\reg,(mipsreg_pc)(\ptr)
	.endm

#else

	.macro sgpr reg,ptr
	sw	$\reg,(mipsreg_regs+\reg*mips_regsize)(\ptr)
	.endm

	.macro lgpr reg,ptr
	lw	$\reg,(mipsreg_regs+\reg*mips_regsize)(\ptr)
	.endm

	.macro slo reg,ptr
	sw	\reg,(mipsreg_lo)(\ptr)
	.endm

	.macro shi reg,ptr
	sw	\reg,(mipsreg_hi)(\ptr)
	.endm

	.macro llo reg,ptr
	lw	\reg,(mipsreg_lo)(\ptr)
	.endm

	.macro lhi reg,ptr
	lw	\reg,(mipsreg_hi)(\ptr)
	.endm

	.macro ssp reg,ptr
	sw	\reg,(mipsreg_regs+29*mips_regsize)(\ptr)
	.endm

	.macro lsp reg,ptr
	lw	\reg,(mipsreg_regs+29*mips_regsize)(\ptr)
	.endm

	.macro sva reg,val
	sw	\reg,\val
	.endm

	.macro lva reg,val
	lw	\reg,\val
	.endm

	.macro mvafc0 gpr,cpr
	mfc0	\gpr,\cpr
	.endm

	.macro mvatc0 gpr,cpr
	mtc0	\gpr,\cpr
	.endm

	.macro lpc reg,ptr
	lw	\reg,(mipsreg_pc)(\ptr)
	.endm

	.macro spc reg,ptr
	sw	\reg,(mipsreg_pc)(\ptr)
	.endm
#endif

#------------------------------------------------------------------------------
# FPU macros.
# The MIPS floating point unit essentially operates in two modes. In the first
# it supplies 32 32bit FP registers that may be paired into 16 64 bit registers.
# In the second it supplies 32 64bit registers. Which mode is to be used depends
# not only on the specific implementation in use, but also on the setting of the
# FR bit in the status register (if it is implemented) and on the expectations of
# the toolchain.			
	
#ifndef CYGPKG_HAL_MIPS_FPU_DEFINED

#ifdef CYGHWR_HAL_MIPS_FPU

#if defined(CYGHWR_HAL_MIPS_FPU_64BIT)
#define sfpr	sdc1
#define lfpr	ldc1
#define CYG_HAL_MIPS_FPU_SR_INIT	0x24000000	
#elif defined(CYGHWR_HAL_MIPS_FPU_32BIT)
#define sfpr	swc1
#define lfpr	lwc1
#define CYG_HAL_MIPS_FPU_SR_INIT	0x20000000		
#else
#error MIPS FPU register size not defined
#endif		

#ifndef CYG_HAL_MIPS_FCSR_INIT
#define CYG_HAL_MIPS_FCSR_INIT 0
#endif

	.macro	hal_fpu_init
	mfc0	v0,status			# Get sr
	la	v1,0xDBFFFFFF			# Clear bits to be changed
	and	v0,v0,v1
	la	v1,CYG_HAL_MIPS_FPU_SR_INIT	# Set the bits we want
	or	v0,v0,v1			# Set sr to required value
	mtc0	v0,status			# return to sr
	nop
	nop
	nop
        la	v0,CYG_HAL_MIPS_FCSR_INIT	# Get initial value for FCR31
	ctc1	v0,$31				# set Fp control reg
	nop
	.endm

	# Save the caller-saved registers as defined by the ABI.
	# These only really need saving during interrupts.
	.macro	hal_fpu_save_caller regs
	cfc1	v0,$31
	sw	v0,mipsreg_fcr31(\regs)
	sfpr	f0,(mipsreg_fpureg+0*mips_fpuregsize)(\regs)
	sfpr	f1,(mipsreg_fpureg+1*mips_fpuregsize)(\regs)
	sfpr	f2,(mipsreg_fpureg+2*mips_fpuregsize)(\regs)
	sfpr	f3,(mipsreg_fpureg+3*mips_fpuregsize)(\regs)
	sfpr	f4,(mipsreg_fpureg+4*mips_fpuregsize)(\regs)
	sfpr	f5,(mipsreg_fpureg+5*mips_fpuregsize)(\regs)
	sfpr	f6,(mipsreg_fpureg+6*mips_fpuregsize)(\regs)
	sfpr	f7,(mipsreg_fpureg+7*mips_fpuregsize)(\regs)
	sfpr	f8,(mipsreg_fpureg+8*mips_fpuregsize)(\regs)
	sfpr	f9,(mipsreg_fpureg+9*mips_fpuregsize)(\regs)
	sfpr	f10,(mipsreg_fpureg+10*mips_fpuregsize)(\regs)
	sfpr	f11,(mipsreg_fpureg+11*mips_fpuregsize)(\regs)
	sfpr	f12,(mipsreg_fpureg+12*mips_fpuregsize)(\regs)
	sfpr	f13,(mipsreg_fpureg+13*mips_fpuregsize)(\regs)
	sfpr	f14,(mipsreg_fpureg+14*mips_fpuregsize)(\regs)
	sfpr	f15,(mipsreg_fpureg+15*mips_fpuregsize)(\regs)
	sfpr	f16,(mipsreg_fpureg+16*mips_fpuregsize)(\regs)
	sfpr	f17,(mipsreg_fpureg+17*mips_fpuregsize)(\regs)
	sfpr	f18,(mipsreg_fpureg+18*mips_fpuregsize)(\regs)
	sfpr	f19,(mipsreg_fpureg+19*mips_fpuregsize)(\regs)
	sfpr	f31,(mipsreg_fpureg+31*mips_fpuregsize)(\regs)
	.endm

	# Save the callee-saved registers as defined by the ABI.
	# These are the only registers that need to be saved
	# across thread switches.
	.macro	hal_fpu_save_callee regs
	sfpr	f20,(mipsreg_fpureg+20*mips_fpuregsize)(\regs)
	sfpr	f21,(mipsreg_fpureg+21*mips_fpuregsize)(\regs)
	sfpr	f22,(mipsreg_fpureg+22*mips_fpuregsize)(\regs)
	sfpr	f23,(mipsreg_fpureg+23*mips_fpuregsize)(\regs)
	sfpr	f24,(mipsreg_fpureg+24*mips_fpuregsize)(\regs)
	sfpr	f25,(mipsreg_fpureg+25*mips_fpuregsize)(\regs)
	sfpr	f26,(mipsreg_fpureg+26*mips_fpuregsize)(\regs)
	sfpr	f27,(mipsreg_fpureg+27*mips_fpuregsize)(\regs)
	sfpr	f28,(mipsreg_fpureg+28*mips_fpuregsize)(\regs)
	sfpr	f29,(mipsreg_fpureg+29*mips_fpuregsize)(\regs)
	sfpr	f30,(mipsreg_fpureg+30*mips_fpuregsize)(\regs)
	.endm

	# General macro to save everything
	.macro	hal_fpu_save regs
	hal_fpu_save_caller \regs
	hal_fpu_save_callee \regs
	.endm

	# Reload the caller-saved registers.
	.macro	hal_fpu_load_caller regs
	lfpr	f0,(mipsreg_fpureg+0*mips_fpuregsize)(\regs)
	lfpr	f1,(mipsreg_fpureg+1*mips_fpuregsize)(\regs)
	lfpr	f2,(mipsreg_fpureg+2*mips_fpuregsize)(\regs)
	lfpr	f3,(mipsreg_fpureg+3*mips_fpuregsize)(\regs)
	lfpr	f4,(mipsreg_fpureg+4*mips_fpuregsize)(\regs)
	lfpr	f5,(mipsreg_fpureg+5*mips_fpuregsize)(\regs)
	lfpr	f6,(mipsreg_fpureg+6*mips_fpuregsize)(\regs)
	lfpr	f7,(mipsreg_fpureg+7*mips_fpuregsize)(\regs)
	lfpr	f8,(mipsreg_fpureg+8*mips_fpuregsize)(\regs)
	lfpr	f9,(mipsreg_fpureg+9*mips_fpuregsize)(\regs)
	lfpr	f10,(mipsreg_fpureg+10*mips_fpuregsize)(\regs)
	lfpr	f11,(mipsreg_fpureg+11*mips_fpuregsize)(\regs)
	lfpr	f12,(mipsreg_fpureg+12*mips_fpuregsize)(\regs)
	lfpr	f13,(mipsreg_fpureg+13*mips_fpuregsize)(\regs)
	lfpr	f14,(mipsreg_fpureg+14*mips_fpuregsize)(\regs)
	lfpr	f15,(mipsreg_fpureg+15*mips_fpuregsize)(\regs)
	lfpr	f16,(mipsreg_fpureg+16*mips_fpuregsize)(\regs)
	lfpr	f17,(mipsreg_fpureg+17*mips_fpuregsize)(\regs)
	lfpr	f18,(mipsreg_fpureg+18*mips_fpuregsize)(\regs)
	lfpr	f19,(mipsreg_fpureg+19*mips_fpuregsize)(\regs)
	lfpr	f31,(mipsreg_fpureg+31*mips_fpuregsize)(\regs)
	lw	v0,mipsreg_fcr31(\regs)
        ctc1	v0,$31
	.endm

	# Reload the callee-saved registers.
	.macro	hal_fpu_load_callee regs
	lfpr	f20,(mipsreg_fpureg+20*mips_fpuregsize)(\regs)
	lfpr	f21,(mipsreg_fpureg+21*mips_fpuregsize)(\regs)
	lfpr	f22,(mipsreg_fpureg+22*mips_fpuregsize)(\regs)
	lfpr	f23,(mipsreg_fpureg+23*mips_fpuregsize)(\regs)
	lfpr	f24,(mipsreg_fpureg+24*mips_fpuregsize)(\regs)
	lfpr	f25,(mipsreg_fpureg+25*mips_fpuregsize)(\regs)
	lfpr	f26,(mipsreg_fpureg+26*mips_fpuregsize)(\regs)
	lfpr	f27,(mipsreg_fpureg+27*mips_fpuregsize)(\regs)
	lfpr	f28,(mipsreg_fpureg+28*mips_fpuregsize)(\regs)
	lfpr	f29,(mipsreg_fpureg+29*mips_fpuregsize)(\regs)
	lfpr	f30,(mipsreg_fpureg+30*mips_fpuregsize)(\regs)
	.endm

	# Reload everything.
	.macro	hal_fpu_load regs
	hal_fpu_load_caller \regs
	hal_fpu_load_callee \regs
	.endm
#else	

	# Default macros for non-fpu implementations
	
	.macro	hal_fpu_init
	.endm
		
	.macro	hal_fpu_save regs
	.endm

	.macro	hal_fpu_save_caller regs
	.endm

	.macro	hal_fpu_save_callee regs
	.endm

	.macro	hal_fpu_load_caller regs
	.endm
	
	.macro	hal_fpu_load_callee regs
	.endm
	
	.macro	hal_fpu_load regs
	.endm
	
#endif
			
#endif	

#------------------------------------------------------------------------------
# MMU macros.
	
#ifndef CYGPKG_HAL_MIPS_MMU_DEFINED

	.macro	hal_mmu_init
	.endm

#endif	

#------------------------------------------------------------------------------
# MEMC macros.
	
#ifndef CYGPKG_HAL_MIPS_MEMC_DEFINED

	.macro	hal_memc_init
	.endm

#endif	
	
#------------------------------------------------------------------------------
# Cache macros.
	
#ifndef CYGPKG_HAL_MIPS_CACHE_DEFINED

#ifdef CYG_HAL_MIPS_R3900
	.macro	hal_cache_init
	mfc0	v0,config		# disable cache in config register
	nop
	nop
	la	v1,0xffffffcf
	and	v0,v0,v1
	mtc0	v0,config
	nop
	nop
	nop
	.endm
#else
	.macro	hal_cache_init

	mfc0	v0,config0		# disable Kseg0 caching in config0 register
	nop
	nop
	la	v1,0xfffffff8
	and	v0,v0,v1
	ori	v0,v0,2
	mtc0	v0,config0
	nop
	nop
	nop

	.endm
#endif

#endif	

#------------------------------------------------------------------------------
# Diagnostics macros.
	
#ifndef CYGPKG_HAL_MIPS_DIAG_DEFINED

	.macro	hal_diag_init
	.endm

	.macro	hal_diag_excpt_start
	.endm

	.macro	hal_diag_intr_start
	.endm

	.macro	hal_diag_restore
	.endm
#endif	

#------------------------------------------------------------------------------
# Timer initialization.
	
#ifndef CYGPKG_HAL_MIPS_TIMER_DEFINED

	.macro	hal_timer_init
	.endm

#endif	

#------------------------------------------------------------------------------
# Monitor initialization.
	
#ifndef CYGPKG_HAL_MIPS_MON_DEFINED

	.macro	hal_mon_init
	.endm

#endif	

#------------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_ARCH_INC
# end of arch.inc