📄 hal_intr.h
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"nop; nop; nop;" \
: \
: "r"(_old_) \
: "$8" \
); \
}
#define HAL_QUERY_INTERRUPTS( _state_ ) \
{ \
asm volatile ( \
"mfc0 %0,$12; nop;" \
"and %0,%0,0x1;" \
: "=r"(_state_) \
: \
: "$8" \
); \
}
#endif // CYGHWR_HAL_INTERRUPT_ENABLE_DISABLE_RESTORE_DEFINED
//--------------------------------------------------------------------------
// Routine to execute DSRs using separate interrupt stack
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
externC void hal_interrupt_stack_call_pending_DSRs(void);
#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
hal_interrupt_stack_call_pending_DSRs()
// these are offered solely for stack usage testing
// if they are not defined, then there is no interrupt stack.
#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
// use them to declare these extern however you want:
// extern char HAL_INTERRUPT_STACK_BASE[];
// extern char HAL_INTERRUPT_STACK_TOP[];
// is recommended
#endif
//--------------------------------------------------------------------------
// Vector translation.
// For chained interrupts we only have a single vector though which all
// are passed. For unchained interrupts we have a vector per interrupt.
#ifndef HAL_TRANSLATE_VECTOR
#if defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = 0
#else
#define HAL_TRANSLATE_VECTOR(_vector_,_index_) (_index_) = (_vector_)
#endif
#endif
//--------------------------------------------------------------------------
// Interrupt and VSR attachment macros
#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
CYG_MACRO_START \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
(_state_) = 0; \
else \
(_state_) = 1; \
CYG_MACRO_END
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
{ \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)HAL_DEFAULT_ISR ) \
{ \
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)_isr_; \
hal_interrupt_data[_index_] = (CYG_ADDRWORD)_data_; \
hal_interrupt_objects[_index_] = (CYG_ADDRESS)_object_; \
} \
}
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
{ \
cyg_uint32 _index_; \
HAL_TRANSLATE_VECTOR( _vector_, _index_ ); \
\
if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)_isr_ ) \
{ \
hal_interrupt_handlers[_index_] = (CYG_ADDRESS)HAL_DEFAULT_ISR; \
hal_interrupt_data[_index_] = 0; \
hal_interrupt_objects[_index_] = 0; \
} \
}
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
*(_pvsr_) = (void (*)())hal_vsr_table[_vector_];
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) CYG_MACRO_START \
if( (void*)_poldvsr_ != NULL) \
*(CYG_ADDRESS *)_poldvsr_ = (CYG_ADDRESS)hal_vsr_table[_vector_]; \
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
CYG_MACRO_END
// This is an ugly name, but what it means is: grab the VSR back to eCos
// internal handling, or if you like, the default handler. But if
// cooperating with GDB and CygMon, the default behaviour is to pass most
// exceptions to CygMon. This macro undoes that so that eCos handles the
// exception. So use it with care.
externC void __default_exception_vsr(void);
externC void __default_interrupt_vsr(void);
externC void __break_vsr_springboard(void);
#define HAL_VSR_SET_TO_ECOS_HANDLER( _vector_, _poldvsr_ ) CYG_MACRO_START \
HAL_VSR_SET( _vector_, _vector_ == CYGNUM_HAL_VECTOR_INTERRUPT \
? (CYG_ADDRESS)__default_interrupt_vsr \
: _vector_ == CYGNUM_HAL_VECTOR_BREAKPOINT \
? (CYG_ADDRESS)__break_vsr_springboard \
: (CYG_ADDRESS)__default_exception_vsr, \
_poldvsr_ ); \
CYG_MACRO_END
//--------------------------------------------------------------------------
// Interrupt controller access
// The default code here simply uses the fields present in the CP0 status
// and cause registers to implement this functionality.
// Beware of nops in this code. They fill delay slots and avoid CP0 hazards
// that might otherwise cause following code to run in the wrong state or
// cause a resource conflict.
#ifndef CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
#define HAL_INTERRUPT_MASK( _vector_ ) \
CYG_MACRO_START \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
CYG_MACRO_START \
asm volatile ( \
"mfc0 $3,$12\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"or $3,$3,$2\n" \
"mtc0 $3,$12\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
CYG_MACRO_START \
asm volatile ( \
"mfc0 $3,$13\n" \
"la $2,0x00000400\n" \
"sllv $2,$2,%0\n" \
"nor $2,$2,$0\n" \
"and $3,$3,$2\n" \
"mtc0 $3,$13\n" \
"nop; nop; nop\n" \
: \
: "r"(_vector_) \
: "$2", "$3" \
); \
CYG_MACRO_END
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ )
#define CYGHWR_HAL_INTERRUPT_CONTROLLER_ACCESS_DEFINED
#endif
//--------------------------------------------------------------------------
// Clock control.
// This code uses the count and compare registers that are present in many
// MIPS variants.
// Beware of nops in this code. They fill delay slots and avoid CP0 hazards
// that might otherwise cause following code to run in the wrong state or
// cause a resource conflict.
#ifndef CYGHWR_HAL_CLOCK_CONTROL_DEFINED
externC CYG_WORD32 cyg_hal_clock_period;
#define CYGHWR_HAL_CLOCK_PERIOD_DEFINED
#define HAL_CLOCK_INITIALIZE( _period_ ) \
CYG_MACRO_START \
asm volatile ( \
"mtc0 $0,$9\n" \
"nop; nop; nop\n" \
"mtc0 %0,$11\n" \
"nop; nop; nop\n" \
: \
: "r"(_period_) \
); \
cyg_hal_clock_period = _period_; \
CYG_MACRO_END
#define HAL_CLOCK_RESET( _vector_, _period_ ) \
CYG_MACRO_START \
asm volatile ( \
"mtc0 $0,$9\n" \
"nop; nop; nop\n" \
"mtc0 %0,$11\n" \
"nop; nop; nop\n" \
: \
: "r"(_period_) \
); \
CYG_MACRO_END
#define HAL_CLOCK_READ( _pvalue_ ) \
CYG_MACRO_START \
register CYG_WORD32 result; \
asm volatile ( \
"mfc0 %0,$9\n" \
: "=r"(result) \
); \
*(_pvalue_) = result; \
CYG_MACRO_END
#define CYGHWR_HAL_CLOCK_CONTROL_DEFINED
#endif
#if defined(CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY) && \
!defined(HAL_CLOCK_LATENCY)
#define HAL_CLOCK_LATENCY( _pvalue_ ) \
CYG_MACRO_START \
register CYG_WORD32 _cval_; \
HAL_CLOCK_READ(&_cval_); \
*(_pvalue_) = _cval_ - cyg_hal_clock_period; \
CYG_MACRO_END
#endif
//--------------------------------------------------------------------------
// Microsecond delay function provided in hal_misc.c
externC void hal_delay_us(int us);
#define HAL_DELAY_US(n) hal_delay_us(n)
//--------------------------------------------------------------------------
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
// End of hal_intr.h
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