var_misc.c

开放源码实时操作系统源码.

//==========================================================================
//
//      var_misc.c
//
//      HAL miscellaneous functions
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov
// Contributors: jskov, jlarmour, nickg
// Date:         2002-01-09
// Purpose:      HAL miscellaneous functions
// Description:  This file contains miscellaneous functions provided by the
//               HAL.
//
//####DESCRIPTIONEND####
//
//===========================================================================

#include <pkgconf/hal.h>

#include <cyg/infra/cyg_type.h>
#include <cyg/infra/cyg_trac.h>         // tracing macros
#include <cyg/infra/cyg_ass.h>          // assertion macros
#include <cyg/infra/diag.h>             // diag_printf

#include <cyg/hal/hal_arch.h>           // HAL header
#include <cyg/hal/hal_cache.h>          // HAL cache
#include <cyg/hal/hal_intr.h>           // HAL interrupts/exceptions

//---------------------------------------------------------------------------
// Initial cache enabling

#ifdef CYGHWR_HAL_SH_CACHE_MODE_WRITE_BACK
# define CACHE_MODE HAL_UCACHE_WRITEBACK_MODE
#else
# define CACHE_MODE HAL_UCACHE_WRITETHRU_MODE
#endif

externC void
cyg_var_enable_caches(void)
{
    // If relying on a ROM monitor do not invalidate the caches as the
    // ROM monitor may have (non-synced) state in the caches.
#if !defined(CYGSEM_HAL_USE_ROM_MONITOR)
    // Initialize cache.
    HAL_UCACHE_INVALIDATE_ALL();    

#ifdef HAL_UCACHE_WRITE_MODE
    // Set cache modes
    HAL_UCACHE_WRITE_MODE(CACHE_MODE);
#endif
#endif
#ifdef CYGHWR_HAL_SH_CACHE_ENABLE
    // Enable cache.
    HAL_UCACHE_ENABLE();
#endif
}

//---------------------------------------------------------------------------
// Interrupt function support

static void
hal_interrupt_set_vectors(void)
{
#if (CYGARC_SH_MOD_INTC == 1)
    // variant specific
    HAL_WRITE_UINT16(CYGARC_REG_VCRDMA0,
                     CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_DMAC0_TE);
    HAL_WRITE_UINT16(CYGARC_REG_VCRDMA1,
                     CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_DMAC1_TE);
    HAL_WRITE_UINT16(CYGARC_REG_VCRWDT, 
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_WDT_ITI)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_REF_CMI));

    HAL_WRITE_UINT16(CYGARC_REG_VCRA,
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_EDMAC_EINT)<<8);
    
    HAL_WRITE_UINT16(CYGARC_REG_VCRC,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_FRT_ICI)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_FRT_OCI));
    HAL_WRITE_UINT16(CYGARC_REG_VCRD,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_FRT_OVI)<<8));
    HAL_WRITE_UINT16(CYGARC_REG_VCRE,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0A)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0B));
    HAL_WRITE_UINT16(CYGARC_REG_VCRF,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0C)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0D));
    HAL_WRITE_UINT16(CYGARC_REG_VCRG,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU0_TGI0V)<<8));
    HAL_WRITE_UINT16(CYGARC_REG_VCRH,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU1_TGI1A)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU1_TGI1B));
    HAL_WRITE_UINT16(CYGARC_REG_VCRI,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU1_TGI1V)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU1_TGI1U));
    HAL_WRITE_UINT16(CYGARC_REG_VCRJ,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU2_TGI2A)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU2_TGI2B));
    HAL_WRITE_UINT16(CYGARC_REG_VCRK,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU2_TGI2V)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_TPU2_TGI2U));
    HAL_WRITE_UINT16(CYGARC_REG_VCRL,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF1_ERI1)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF1_RXI1));
    HAL_WRITE_UINT16(CYGARC_REG_VCRM,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF1_BRI1)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF1_TXI1));
    HAL_WRITE_UINT16(CYGARC_REG_VCRN,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF2_ERI2)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF2_RXI2));
    HAL_WRITE_UINT16(CYGARC_REG_VCRO,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF2_BRI2)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SCIF2_TXI2));
    HAL_WRITE_UINT16(CYGARC_REG_VCRP,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO0_RERI0)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO0_TERI0));
    HAL_WRITE_UINT16(CYGARC_REG_VCRQ,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO0_RDFI0)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO0_TDEI0));
    HAL_WRITE_UINT16(CYGARC_REG_VCRR,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO1_RERI1)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO1_TERI1));
    HAL_WRITE_UINT16(CYGARC_REG_VCRS,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO1_RDFI1)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO1_TDEI1));
    HAL_WRITE_UINT16(CYGARC_REG_VCRT,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO2_RERI2)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO2_TERI2));
    HAL_WRITE_UINT16(CYGARC_REG_VCRU,
                     ((CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO2_RDFI2)<<8) |
                     (CYGNUM_HAL_INTERRUPT_HW_EXC_BASE+CYGNUM_HAL_INTERRUPT_SIO2_TDEI2));

#elif (CYGARC_SH_MOD_INTC == 2)
    /* Hardwired vectors */
#else
# error "No priority handling for INTC variant"
#endif
}

externC cyg_uint8 cyg_hal_ILVL_table[];
externC cyg_uint8 cyg_hal_IMASK_table[];

static void
hal_interrupt_update_level(int vector)
{
    cyg_uint16 iprX;
    int level;

    level = cyg_hal_IMASK_table[vector] ? cyg_hal_ILVL_table[vector] : 0;

    switch( (vector) ) {
#if (CYGARC_SH_MOD_INTC == 1)
        /* IPRA */
    case CYGNUM_HAL_INTERRUPT_DMAC0_TE:
    case CYGNUM_HAL_INTERRUPT_DMAC1_TE:
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
        iprX &= ~CYGARC_REG_IPRA_DMAC_MASK;
        iprX |= (level)*CYGARC_REG_IPRA_DMAC_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_WDT_ITI:
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
        iprX &= ~CYGARC_REG_IPRA_WDT_MASK;
        iprX |= (level)*CYGARC_REG_IPRA_WDT_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
        break;

        /* This vector can not be configured */
    case CYGNUM_HAL_INTERRUPT_REF_CMI:
        break;

        /* IPRB */
    case CYGNUM_HAL_INTERRUPT_EDMAC_EINT:
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
        iprX &= ~CYGARC_REG_IPRB_EDMAC_MASK;
        iprX |= (level)*CYGARC_REG_IPRB_EDMAC_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_FRT_ICI:
    case CYGNUM_HAL_INTERRUPT_FRT_OCI:
    case CYGNUM_HAL_INTERRUPT_FRT_OVI:
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
        iprX &= ~CYGARC_REG_IPRB_FRT_MASK;
        iprX |= (level)*CYGARC_REG_IPRB_FRT_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
        break;

#ifndef CYGHWR_HAL_SH_IRQ_USE_IRQLVL
        /* IPRC */
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
        iprX &= ~CYGARC_REG_IPRC_IRQ0_MASK;
        iprX |= (level)*CYGARC_REG_IPRC_IRQ0_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
        iprX &= ~CYGARC_REG_IPRC_IRQ1_MASK;
        iprX |= (level)*CYGARC_REG_IPRC_IRQ1_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
        iprX &= ~CYGARC_REG_IPRC_IRQ2_MASK;
        iprX |= (level)*CYGARC_REG_IPRC_IRQ2_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
        iprX &= ~CYGARC_REG_IPRC_IRQ3_MASK;
        iprX |= (level)*CYGARC_REG_IPRC_IRQ3_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
        break;
#else
    case CYGNUM_HAL_INTERRUPT_LVL0 ... CYGNUM_HAL_INTERRUPT_LVL3:
        /* Cannot change levels */
        break;                                                           
#endif
        /* IPRD */
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0A:
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0B:
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0C:
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0D:
    case CYGNUM_HAL_INTERRUPT_TPU0_TGI0V:
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
        iprX &= ~CYGARC_REG_IPRD_TPU0_MASK;
        iprX |= (level)*CYGARC_REG_IPRD_TPU0_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_TPU1_TGI1A:
    case CYGNUM_HAL_INTERRUPT_TPU1_TGI1B:
    case CYGNUM_HAL_INTERRUPT_TPU1_TGI1V:
    case CYGNUM_HAL_INTERRUPT_TPU1_TGI1U:
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
        iprX &= ~CYGARC_REG_IPRD_TPU1_MASK;
        iprX |= (level)*CYGARC_REG_IPRD_TPU1_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_TPU2_TGI2A:
    case CYGNUM_HAL_INTERRUPT_TPU2_TGI2B:
    case CYGNUM_HAL_INTERRUPT_TPU2_TGI2V:
    case CYGNUM_HAL_INTERRUPT_TPU2_TGI2U:
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
        iprX &= ~CYGARC_REG_IPRD_TPU2_MASK;
        iprX |= (level)*CYGARC_REG_IPRD_TPU2_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_SCIF1_ERI1:
    case CYGNUM_HAL_INTERRUPT_SCIF1_RXI1:
    case CYGNUM_HAL_INTERRUPT_SCIF1_BRI1:
    case CYGNUM_HAL_INTERRUPT_SCIF1_TXI1:
        HAL_READ_UINT16(CYGARC_REG_IPRD, iprX);
        iprX &= ~CYGARC_REG_IPRD_SCIF1_MASK;
        iprX |= (level)*CYGARC_REG_IPRD_SCIF1_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRD, iprX);
        break;

        /* IPRE */
    case CYGNUM_HAL_INTERRUPT_SCIF2_ERI2:
    case CYGNUM_HAL_INTERRUPT_SCIF2_RXI2:
    case CYGNUM_HAL_INTERRUPT_SCIF2_BRI2:
    case CYGNUM_HAL_INTERRUPT_SCIF2_TXI2:
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
        iprX &= ~CYGARC_REG_IPRE_SCIF2_MASK;
        iprX |= (level)*CYGARC_REG_IPRE_SCIF2_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_SIO0_RERI0:
    case CYGNUM_HAL_INTERRUPT_SIO0_TERI0:
    case CYGNUM_HAL_INTERRUPT_SIO0_RDFI0:
    case CYGNUM_HAL_INTERRUPT_SIO0_TDEI0:
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
        iprX &= ~CYGARC_REG_IPRE_SIO0_MASK;
        iprX |= (level)*CYGARC_REG_IPRE_SIO0_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_SIO1_RERI1:
    case CYGNUM_HAL_INTERRUPT_SIO1_TERI1:
    case CYGNUM_HAL_INTERRUPT_SIO1_RDFI1:
    case CYGNUM_HAL_INTERRUPT_SIO1_TDEI1:
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
        iprX &= ~CYGARC_REG_IPRE_SIO1_MASK;
        iprX |= (level)*CYGARC_REG_IPRE_SIO1_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_SIO2_RERI2:
    case CYGNUM_HAL_INTERRUPT_SIO2_TERI2:
    case CYGNUM_HAL_INTERRUPT_SIO2_RDFI2:
    case CYGNUM_HAL_INTERRUPT_SIO2_TDEI2:
        HAL_READ_UINT16(CYGARC_REG_IPRE, iprX);
        iprX &= ~CYGARC_REG_IPRE_SIO2_MASK;
        iprX |= (level)*CYGARC_REG_IPRE_SIO2_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRE, iprX);
        break;
#elif (CYGARC_SH_MOD_INTC == 2)

        /* IPRA */
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ0:
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
        iprX &= ~CYGARC_REG_IPRA_IRQ0_MASK;
        iprX |= (level)*CYGARC_REG_IPRA_IRQ0_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ1:
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
        iprX &= ~CYGARC_REG_IPRA_IRQ1_MASK;
        iprX |= (level)*CYGARC_REG_IPRA_IRQ1_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ2:
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
        iprX &= ~CYGARC_REG_IPRA_IRQ2_MASK;
        iprX |= (level)*CYGARC_REG_IPRA_IRQ2_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ3:
        HAL_READ_UINT16(CYGARC_REG_IPRA, iprX);
        iprX &= ~CYGARC_REG_IPRA_IRQ3_MASK;
        iprX |= (level)*CYGARC_REG_IPRA_IRQ3_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRA, iprX);
        break;

        /* IPRB */
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ4:
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
        iprX &= ~CYGARC_REG_IPRB_IRQ4_MASK;
        iprX |= (level)*CYGARC_REG_IPRB_IRQ4_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ5:
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
        iprX &= ~CYGARC_REG_IPRB_IRQ5_MASK;
        iprX |= (level)*CYGARC_REG_IPRB_IRQ5_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ6:
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
        iprX &= ~CYGARC_REG_IPRB_IRQ6_MASK;
        iprX |= (level)*CYGARC_REG_IPRB_IRQ6_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_IRQ_IRQ7:
        HAL_READ_UINT16(CYGARC_REG_IPRB, iprX);
        iprX &= ~CYGARC_REG_IPRB_IRQ7_MASK;
        iprX |= (level)*CYGARC_REG_IPRB_IRQ7_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRB, iprX);
        break;

        /* IPRB */
    case CYGNUM_HAL_INTERRUPT_DMAC0_DEI0:
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
        iprX &= ~CYGARC_REG_IPRC_DMAC0_MASK;
        iprX |= (level)*CYGARC_REG_IPRC_DMAC0_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_DMAC1_DEI1:
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
        iprX &= ~CYGARC_REG_IPRC_DMAC1_MASK;
        iprX |= (level)*CYGARC_REG_IPRC_DMAC1_PRI1;
        HAL_WRITE_UINT16(CYGARC_REG_IPRC, iprX);
        break;
    case CYGNUM_HAL_INTERRUPT_DMAC2_DEI2:
        HAL_READ_UINT16(CYGARC_REG_IPRC, iprX);
        iprX &= ~CYGARC_REG_IPRC_DMAC2_MASK;
        iprX |= (level)*CYGARC_REG_IPRC_DMAC2_PRI1;