via_rhine.h

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#ifndef CYGONCE_DEVS_ETH_VIA_RHINE_H
#define CYGONCE_DEVS_ETH_VIA_RHINE_H
//==========================================================================
//
//      via_rhine.h
//
//      VIA Rhine Ethernet chip
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    jskov
// Contributors: jskov
// Date:         2001-05-30
// Purpose:      Hardware description of VIA Rhine series.
// Description:  
//
//####DESCRIPTIONEND####
//
//==========================================================================

#include <cyg/hal/hal_io.h>
#include <cyg/io/pci_hw.h>             // HAL_PCI_ macros

//------------------------------------------------------------------------
// Get macros from platform header
#define __WANT_CONFIG
#include CYGDAT_DEVS_ETH_VIA_RHINE_INL
#undef  __WANT_CONFIG

//------------------------------------------------------------------------
// Set to perms of:
// 0 disables all debug output
// 1 for process debug output
// 2 for added data IO output: get_reg, put_reg
// 4 for packet allocation/free output
// 8 for only startup status, so we can tell we're installed OK
#define DEBUG 0x00

#if DEBUG & 1
# define DEBUG_FUNCTION() do { diag_printf("%s\n", __FUNCTION__); } while (0)
#else
# define DEBUG_FUNCTION() do {} while(0)
#endif

// ------------------------------------------------------------------------
// Macros for keeping track of statistics
#if defined(ETH_DRV_GET_IF_STATS) || defined (ETH_DRV_GET_IF_STATS_UD)
#define KEEP_STATISTICS
#endif

#ifdef KEEP_STATISTICS
#define INCR_STAT( _x_ )        (cpd->stats. _x_ ++)
#else
#define INCR_STAT( _x_ )        CYG_EMPTY_STATEMENT
#endif

//------------------------------------------------------------------------
// Cache translation
#ifndef CYGARC_UNCACHED_ADDRESS
# define CYGARC_UNCACHED_ADDRESS(x) (x)
#endif

//------------------------------------------------------------------------
// Address translation
#ifndef HAL_PCI_CPU_TO_BUS
# error "HAL PCI support must define translation macros"
#endif

//------------------------------------------------------------------------
// Macros for accessing structure elements

#define _SU8( _base_, _offset_) \
        *((volatile cyg_uint8 *)((CYG_ADDRWORD)_base_+(_offset_)))
#define _SU16( _base_, _offset_) \
        *((volatile cyg_uint16 *)((CYG_ADDRWORD)_base_+(_offset_)))
#define _SU32( _base_, _offset_) \
        *((volatile cyg_uint32 *)((CYG_ADDRWORD)_base_+(_offset_)))

#define _SI8( _base_, _offset_) \
        *((volatile cyg_int8 *)((CYG_ADDRWORD)_base_+(_offset_)))
#define _SI16( _base_, _offset_) \
        *((volatile cyg_int16 *)((CYG_ADDRWORD)_base_+(_offset_)))
#define _SI32( _base_, _offset_) \
        *((volatile cyg_int32 *)((CYG_ADDRWORD)_base_+(_offset_)))

// ------------------------------------------------------------------------
// Macros for accessing controller registers
#ifndef HAL_PCI_IO_READ_UINT8
# define HAL_PCI_IO_READ_UINT8(addr, datum)   HAL_READ_UINT8(addr, datum)
# define HAL_PCI_IO_WRITE_UINT8(addr, datum)  HAL_WRITE_UINT8(addr, datum)
# define HAL_PCI_IO_READ_UINT16(addr, datum)  HAL_READ_UINT16(addr, datum)
# define HAL_PCI_IO_WRITE_UINT16(addr, datum) HAL_WRITE_UINT16(addr, datum)
# define HAL_PCI_IO_READ_UINT32(addr, datum)  HAL_READ_UINT32(addr, datum)
# define HAL_PCI_IO_WRITE_UINT32(addr, datum) HAL_WRITE_UINT32(addr, datum)
#endif

// ------------------------------------------------------------------------
// Control registers
#define RHINE_PAR0         0x00
#define RHINE_PAR1         0x01
#define RHINE_PAR2         0x02
#define RHINE_PAR3         0x03
#define RHINE_PAR4         0x04
#define RHINE_PAR5         0x05

#define RHINE_RCR          0x06
#define RHINE_TCR          0x07
#define RHINE_CR0          0x08
#define RHINE_CR1          0x09

#define RHINE_ISR          0x0c         // 16 bit
#define RHINE_IMR          0x0e         // 16 bit

#define RHINE_CUR_RX       0x18
#define RHINE_CUR_TX       0x1c


#define RHINE_PHYADR       0x6c
#define RHINE_MIISR        0x6d
#define RHINE_BCR0         0x6e
#define RHINE_BCR1         0x6f
#define RHINE_MIICR        0x70
#define RHINE_MIIAD        0x71
#define RHINE_MIIDATA      0x72         // 16 bit


#define RHINE_EECSR        0x74

#define RHINE_CFGA         0x78
#define RHINE_CFGB         0x79
#define RHINE_CFGC         0x7a
#define RHINE_CFGD         0x7b

#define RHINE_STICKYHW     0x83
#define RHINE_WOL_CR_CLR   0xa4
#define RHINE_WOL_CG_CLR   0xa7
#define RHINE_PWR_CSR_CLR  0xac

#define RHINE_RCR_RRSF     0x80
#define RHINE_RCR_RFT_64   0x00
#define RHINE_RCR_RFT_SF   0x60
#define RHINE_RCR_PRO      0x10
#define RHINE_RCR_AB       0x08
#define RHINE_RCR_AM       0x04
#define RHINE_RCR_AR       0x02
#define RHINE_RCR_SEP      0x01

#define RHINE_TCR_RTSF     0x80
#define RHINE_TCR_TFT_64   0x00
#define RHINE_TCR_TFT_SF   0x60
#define RHINE_TCR_OFFSET   0x08
#define RHINE_TCR_LB1      0x04
#define RHINE_TCR_LB0      0x02

#define RHINE_CR0_RDMD       0x40
#define RHINE_CR0_TDMD       0x20
#define RHINE_CR0_TXON       0x10
#define RHINE_CR0_RXON       0x08
#define RHINE_CR0_STOP       0x04
#define RHINE_CR0_STRT       0x02
#define RHINE_CR0_INIT       0x01

#define RHINE_CR1_SRST       0x80
#define RHINE_CR1_DPOLL      0x08
#define RHINE_CR1_FDX        0x04
#define RHINE_CR1_ETEN       0x02
#define RHINE_CR1_EREN       0x01

#define RHINE_ISR_KEYI       0x8000
#define RHINE_ISR_SRCI       0x4000
#define RHINE_ISR_ABTI       0x2000
#define RHINE_ISR_NORBF      0x1000
#define RHINE_ISR_PKRACE     0x0800
#define RHINE_ISR_OVFI       0x0400
#define RHINE_ISR_ETI        0x0200
#define RHINE_ISR_ERI        0x0100
#define RHINE_ISR_CNT        0x0080
#define RHINE_ISR_BE         0x0040
#define RHINE_ISR_RU         0x0020
#define RHINE_ISR_TU         0x0010
#define RHINE_ISR_TXE        0x0008
#define RHINE_ISR_RXE        0x0004
#define RHINE_ISR_PTX        0x0002
#define RHINE_ISR_PRX        0x0001

#define RHINE_IMR_KEYI       0x8000
#define RHINE_IMR_SRCI       0x4000
#define RHINE_IMR_ABTI       0x2000
#define RHINE_IMR_NORBF      0x1000
#define RHINE_IMR_PKRACE     0x0800
#define RHINE_IMR_OVFI       0x0400
#define RHINE_IMR_ETI        0x0200
#define RHINE_IMR_ERI        0x0100
#define RHINE_IMR_CNT        0x0080
#define RHINE_IMR_BE         0x0040
#define RHINE_IMR_RU         0x0020
#define RHINE_IMR_TU         0x0010
#define RHINE_IMR_TXE        0x0008
#define RHINE_IMR_RXE        0x0004
#define RHINE_IMR_PTX        0x0002
#define RHINE_IMR_PRX        0x0001