enetphy.h

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// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 2002 Gary Thomas
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/*------------------------------------------------------------------    
*
* FILE: EnetPHY.c
*
* DESCRIPTION:   LXT970a driver header file
*
*
* Modified for MPC8260 VADS board
*-------------------------------------------------------------------*/

#ifndef _EnetPHY_H 
#define _EnetPHY_H

#include "types.h"

// Board control and status registers
typedef struct bcsr {
  UINT32  bcsr0; 
  UINT32  bcsr1;
  UINT32  bcsr2;
  UINT32  bcsr3;
} t_BCSR;

// Fast ethernet enable/reset pins on bcsr
#define FETHIEN_ 0x08000000
#define FETHRST_ 0x04000000


/**************************/
/* The API for PHY Device */
/**************************/

void   EnableResetPHY(volatile t_BCSR *pBCSR);
UINT16 InitEthernetPHY(VUINT32* pdir, VUINT32* pdat, UINT16 link);
UINT16 EthernetPHYInterruptHandler(void);
void   EnablePHYinterrupt(UINT8 enable);
UINT16 LinkTestPHY(void);


typedef enum MDIORW {READ, WRITE} MDIORW;


#define LINKERROR   0xFFFF
#define NOTLINKED   0x0000
#define TEN_HD      0x0020
#define TEN_FD      0x0040
#define HUNDRED_HD  0x0080
#define HUNDRED_FD  0x0100

#define MD_TEST_FRAME 0xDEAD

//8260 VADS Pin Connections
#define MDIO_PIN_MASK 0x00400000        //PC9  for 8260 VADS
#define MDC_PIN_MASK  0x00200000        //PC10 for 8260 VADS

//#define MDIO_PIN_MASK 0x00000200        //PC9  for 8260 VADS
//#define MDC_PIN_MASK  0x00000400        //PC10 for 8260 VADS

//IEEE 802.3 PHY Register Definitions
#define CONTROL_REG		 0
#define STATUS_REG		 1
#define PHY_ID_REG_A		 2
#define PHY_ID_REG_B		 3
#define AUTONEG_AD_REG		 4
#define AUTONEG_LINKPARTNER_REG  5
#define AUTONEG_EXP_REG		 6

//LXT970a Specific Register Definitions
#define MIRROR_REG		16
#define INT_EN_REG		17
#define INT_STAT_REG		18
#define CONFIG_REG	        19
#define CHIP_STAT_REG	        20

//Clock Timing Control
#define MDC_HOLD_TIME           50

#endif