netarm_hal.patch
来自「开放源码实时操作系统源码.」· PATCH 代码 · 共 535 行 · 第 1/2 页
PATCH
535 行
diff -Naur orig/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl new/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl
--- orig/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl 2004-11-29 17:35:46.000000000 +0100
+++ new/hal/arm/netarm/current/cdl/hal_arm_netarm.cdl 2005-03-10 14:54:13.903367200 +0100
@@ -18,6 +18,26 @@
puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_arm_netarm.h>"
}
+ cdl_option CYGSEM_HAL_INSTRUCTION_CACHE_SETS {
+ display "Sets for Instruction Cache"
+ parent CYGPKG_HAL_CACHE_CONTROL
+ active_if CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
+ flavor data
+ legal_values 0 to 15
+ default_value 0xc
+ description "MSB: SET1 | SET2 | SET3 | SET4"
+ }
+
+ cdl_option CYGSEM_HAL_DATA_CACHE_SETS {
+ display "Sets for Data Cache"
+ parent CYGPKG_HAL_CACHE_CONTROL
+ active_if CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
+ flavor data
+ legal_values 0 to 15
+ default_value 0x3
+ description "MSB: SET1 | SET2 | SET3 | SET4"
+ }
+
cdl_component CYG_HAL_STARTUP {
display "Startup type"
flavor data
diff -Naur orig/hal/arm/netarm/current/include/hal_cache.h new/hal/arm/netarm/current/include/hal_cache.h
--- orig/hal/arm/netarm/current/include/hal_cache.h 2004-11-29 17:35:46.000000000 +0100
+++ new/hal/arm/netarm/current/include/hal_cache.h 2005-03-10 14:41:51.032173600 +0100
@@ -19,25 +19,57 @@
#define HAL_ICACHE_WAYS 4 // Associativity of the cache
#define HAL_ICACHE_LINE_SIZE 4 // Size of a cache line
-#define HAL_ICACHE_BASE 0x08000000
-#define HAL_ICACHE_MASK 0xfe000000
+#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_RAM)
+ #define HAL_ICACHE_BASE 0x04000000
+ #define HAL_DCACHE_BASE 0x08000000
+#else
+ #define HAL_ICACHE_BASE 0x02000000
+ #define HAL_DCACHE_BASE 0x04000000
+#endif
+
+#define HAL_ICACHE_MASK 0xff000000
+#define HAL_DCACHE_MASK 0xff000000
+
+
+#ifdef CYGSEM_HAL_ENABLE_ICACHE_ON_STARTUP
+ #define HAL_ICACHE_ENABLE() \
+ { \
+ *(CCR0)=(HAL_ICACHE_BASE) | \
+ (HAL_ICACHE_MASK >> 8) | \
+ (CCR_ENABLE) | \
+ (1 << 11) | \
+ (CYGSEM_HAL_INSTRUCTION_CACHE_SETS); \
+ }
+#else
+ #define HAL_ICACHE_ENABLE() (*(CCR0)=0)
+#endif
-#define HAL_ICACHE_ENABLE() \
+#ifdef CYGSEM_HAL_ENABLE_DCACHE_ON_STARTUP
+ #define HAL_DCACHE_ENABLE() \
+ { \
+ *(CCR1)=(HAL_DCACHE_BASE) | \
+ (HAL_DCACHE_MASK >> 8) | \
+ (CCR_ENABLE) | \
+ (1 << 11) | \
+ (CYGSEM_HAL_DATA_CACHE_SETS); \
+ }
+#else
+ #define HAL_DCACHE_ENABLE() (*(CCR1)=0)
+#endif
+
+#define HAL_CACHE_ENABLE() \
{ \
unsigned int *p; \
int i; \
\
*(SYSCON)|=SYSCON_CINIT|SYSCON_CACHE; \
p=(unsigned int *)0xfff00000; \
- for(i=0;i<(0x2000/4);i++,p++) \
+ for(i=0;i<(0x4000/4);i++,p++) \
*p=0; \
\
- *(SYSCON)&=~(SYSCON_CINIT); \
- *(CCR0)=(HAL_ICACHE_BASE) | \
- (HAL_ICACHE_MASK >> 8) | \
- (CCR_ENABLE) | \
- (CCR_SET1 | CCR_SET2 | CCR_SET3 | CCR_SET4); \
- *(CCR1)=0; \
+ HAL_ICACHE_ENABLE(); \
+ HAL_DCACHE_ENABLE(); \
+ \
*(SYSCON)|=SYSCON_CACHE; \
*(SYSCON)&=~SYSCON_WB; \
}
@@ -45,17 +77,25 @@
#define HAL_ICACHE_DISABLE() \
{ \
*(CCR0)=0; \
- *(SYSCON)&=~SYSCON_CACHE; \
+ if (HAL_DCACHE_IS_ENABLED == 0) \
+ *(SYSCON)&=~SYSCON_CACHE; \
}
-#define HAL_ICACHE_IS_ENABLED(_state_) _state_ = ((*(CCR0) & CCR_ENABLE) >> 15)
+#define HAL_DCACHE_DISABLE() \
+{ \
+ *(CCR1)=0; \
+ if (HAL_ICACHE_IS_ENABLED == 0) \
+ *(SYSCON)&=~SYSCON_CACHE; \
+}
+
+#define HAL_ICACHE_IS_ENABLED ((*(CCR0) & CCR_ENABLE) >> 15)
-#define HAL_ICACHE_INVALIDATE_ALL() \
+#define HAL_CACHE_INVALIDATE_ALL() \
{ \
unsigned *p; \
*(SYSCON)|=SYSCON_CINIT; \
for(p=(unsigned int*)0xfff00000; \
- (unsigned int)p<0xfff02000; \
+ (unsigned int)p<0xfff04000; \
p++) \
*p=0; \
\
@@ -64,25 +104,13 @@
#define HAL_ICACHE_SYNC()
-#define HAL_ICACHE_PURGE_ALL() HAL_ICACHE_INVALIDATE_ALL()
-
-#define HAL_DCACHE_LINE_SIZE 0
-#define HAL_DCACHE_WAYS 0
-#define HAL_DCACHE_SETS 0
-
-#define HAL_DCACHE_ENABLE()
+#define HAL_CACHE_PURGE_ALL() HAL_ICACHE_INVALIDATE_ALL()
-#define HAL_DCACHE_DISABLE()
-
-#define HAL_DCACHE_INVALIDATE_ALL()
+#define HAL_DCACHE_LINE_SIZE 4
+#define HAL_DCACHE_WAYS 4
#define HAL_DCACHE_SYNC()
-#define HAL_DCACHE_IS_ENABLED(_state_) 0
-
-#define HAL_DCACHE_FLUSH( _base_ , _size_ )
-
-#define HAL_DCACHE_STORE( _base_ , _size_ )
+#define HAL_DCACHE_IS_ENABLED ((*(CCR1) & CCR_ENABLE) >> 15)
#endif
-
diff -Naur orig/hal/arm/netarm/current/include/hal_platform_setup.h new/hal/arm/netarm/current/include/hal_platform_setup.h
--- orig/hal/arm/netarm/current/include/hal_platform_setup.h 2004-11-29 17:35:46.000000000 +0100
+++ new/hal/arm/netarm/current/include/hal_platform_setup.h 2005-03-15 12:20:27.760534400 +0100
@@ -19,7 +19,7 @@
// Usage: #include <cyg/hal/hal_platform_setup.h>
//
//####DESCRIPTIONEND####
-//
+//
//===========================================================================*/
#include <pkgconf/system.h> // System-wide configuration info
@@ -34,15 +34,31 @@
bic r0,r0, #((\x & 3)<<1); \
str r0,[r1]
-#if defined(CYG_HAL_STARTUP_ROMRAM)
+#if defined(CYG_HAL_STARTUP_ROMRAM)
#define HAL_FLASH_PHYS_ADDR 0x02000000
-#define UNMAPPED(x) ((x)-0x08000000)
+#define UNMAPPED(x) ((x)-0x04000000)
#elif defined(CYG_HAL_STARTUP_ROM)
#define HAL_FLASH_PHYS_ADDR 0x02000000
#define UNMAPPED(x) ((x)-0x02000000)
#endif
.macro PLATFORM_SETUP1
-
+
+ ldr r1,=0xffb0000c // software reset
+ ldr r0,=0x00000123
+ str r0,[r1]
+ ldr r0,=0x00000321
+ str r0,[r1]
+
+ mov r0,#1000
+loop:
+ sub r0,r0,#1
+ cmp r0,#0
+ bne loop
+
+ ldr r0,=0x00000123
+ str r0,[r1]
+ ldr r0,=0x00000321
+ str r0,[r1]
#if defined(CYG_HAL_STARTUP_ROMRAM) || defined(CYG_HAL_STARTUP_ROM)
mov r1,#0xff000000
@@ -51,7 +67,11 @@
ldr r0,=0x4004a800 /* System control register */
str r0,[r1]
- mov r0,#0 /* PLL config */
+#ifdef CYG_HAL_STARTUP_ROM /* PLL config */
+ mov r0,#0
+#else
+ ldr r0,=0x09000e1e
+#endif
str r0,[r1,#8]
ldr r0,=0xfff00000 /* PORT A mode & dir */
@@ -64,7 +84,7 @@
str r0,[r1,#0x28]
add r1,r1,#0x100000 /* Setup MEM Module base addr */
-
+
ldr r0,=0x148C0000 /* Memory Module Config register */
str r0,[r1]
@@ -79,7 +99,7 @@
ldr r0,=0xf3f00304 /* CS0 Option register */
str r0,[r1,#0x14]
- ldr r0,=0x02000001 /* CS0 Base Address register */
+ ldr r0,=0x02000001 /* CS0 Base Address register */
str r0,[r1,#0x10]
mov pc,r2 /* Jump to new flash base */
@@ -92,7 +112,7 @@
/* Configure SDRAM */
- ldr r0,=0xf38000b0 /* CS1 Option register, BLEN=11 */
+ ldr r0,=0xf3000070 /* CS1 Option register, BLEN=11 */
str r0,[r1,#0x24]
ldr r0,=0x0000022d /* CS1 Base Address register */
@@ -110,7 +130,7 @@
#if defined(CYG_HAL_STARTUP_ROMRAM)
mov r1,#0
mov r2,#HAL_FLASH_PHYS_ADDR
- ldr r3,=(__heap1 - 0x04000000 + HAL_FLASH_PHYS_ADDR)
+ ldr r3,=(__heap1 - 0x08000000 + HAL_FLASH_PHYS_ADDR)
mov r4,#0
mov r6,#0
@@ -129,11 +149,11 @@
nop
nop
nop
-30:
+30:
#endif
#endif
.endm
-
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