amd_pcnet.h
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#define PCNET_ANR_PHYSTAT_LINK 0x0004
#define PCNET_ANR_AAR_100_FD 0x0100
#define PCNET_ANR_AAR_100_HD 0x0080
#define PCNET_ANR_AAR_100 0x0180
#define PCNET_ANR_AAR_10_FD 0x0040
#define PCNET_ANR_AAR_10_HD 0x0020
#define PCNET_ANR_AAR_10 0x0060
//----------------------------------------------------------------------------
// Receive buffer Descriptor
#if 1
#define PCNET_RD_PTR 0x00 // 32 bit
#define PCNET_RD_BLEN 0x04 // 16 bit (2's complement, negative)
#define PCNET_RD_MLEN 0x06 // 16 bit
#define PCNET_RD_SIZE 0x08
#define PCNET_RD_PTR_OWN 0x80000000
#define PCNET_RD_PTR_ERR 0x40000000
#define PCNET_RD_PTR_FRAM 0x20000000
#define PCNET_RD_PTR_OFLO 0x10000000
#define PCNET_RD_PTR_CRC 0x08000000
#define PCNET_RD_PTR_BUFF 0x04000000
#define PCNET_RD_PTR_STP 0x02000000
#define PCNET_RD_PTR_ENP 0x01000000
#define PCNET_RD_PTR_MASK 0x00ffffff
#else
#define PCNET_RD_PTR 0x00
#define PCNET_RD_BLEN 0x04
#define PCNET_RD_MLEN 0x08
#define PCNET_RD_USER 0x0c
#define PCNET_RD_SIZE 0x10
#define PCNET_RD_BLEN_OWN 0x80000000
#define PCNET_RD_BLEN_ERR 0x40000000
#define PCNET_RD_BLEN_FRAM 0x20000000
#define PCNET_RD_BLEN_OFLO 0x10000000
#define PCNET_RD_BLEN_CRC 0x08000000
#define PCNET_RD_BLEN_BUFF 0x04000000
#define PCNET_RD_BLEN_STP 0x02000000
#define PCNET_RD_BLEN_ENP 0x01000000
#define PCNET_RD_BLEN_BPE 0x00800000
#define PCNET_RD_BLEN_PAM 0x00400000
#define PCNET_RD_BLEN_LAFM 0x00200000
#define PCNET_RD_BLEN_BAM 0x00100000
#define PCNET_RD_BLEN_MASK 0x0000ffff
#endif
// Transmit buffer Descriptor
#if 1
#define PCNET_TD_PTR 0x00 // 32 bit
#define PCNET_TD_LEN 0x04 // 16 bit (2's complement, negative)
#define PCNET_TD_MISC 0x06 // 16 bit
#define PCNET_TD_SIZE 0x08
#define PCNET_TD_PTR_OWN 0x80000000
#define PCNET_TD_PTR_ERR 0x40000000
#define PCNET_TD_PTR_ADD_FCS 0x20000000
#define PCNET_TD_PTR_MORE 0x10000000
#define PCNET_TD_PTR_ONE 0x08000000
#define PCNET_TD_PTR_DEF 0x04000000
#define PCNET_TD_PTR_STP 0x02000000
#define PCNET_TD_PTR_ENP 0x01000000
#define PCNET_TD_PTR_MASK 0x00ffffff
#else
#define PCNET_TD_PTR 0x00
#define PCNET_TD_LEN 0x04
#define PCNET_TD_MISC 0x08
#define PCNET_TD_USER 0x0c
#define PCNET_TD_SIZE 0x10
#define PCNET_TD_LEN_OWN 0x80000000
#define PCNET_TD_LEN_ERR 0x40000000
#define PCNET_TD_LEN_ADD_FCS 0x20000000
#define PCNET_TD_LEN_MORE 0x10000000
#define PCNET_TD_LEN_ONE 0x08000000
#define PCNET_TD_LEN_DEF 0x04000000
#define PCNET_TD_LEN_STP 0x02000000
#define PCNET_TD_LEN_ENP 0x01000000
#define PCNET_TD_LEN_BPE 0x00800000
#define PCNET_TD_LEN_MASK 0x0000ffff
#define PCNET_TD_FLAGS_BUFF 0x80000000
#define PCNET_TD_FLAGS_UFLO 0x40000000
#define PCNET_TD_FLAGS_EX_DEF 0x20000000
#define PCNET_TD_FLAGS_LCOL 0x10000000
#define PCNET_TD_FLAGS_LCAR 0x08000000
#define PCNET_TD_FLAGS_RTRY 0x04000000
#define PCNET_TD_FLAGS_TRC_MASK 0x0000000f
#endif
#define PCNET_TD_MISC_BUFF 0x8000
#define PCNET_TD_MISC_UFLO 0x4000
#define PCNET_TD_MISC_EXDEF 0x2000
#define PCNET_TD_MISC_LCOL 0x1000
#define PCNET_TD_MISC_LCAR 0x0800
#define PCNET_TD_MISC_RTRY 0x0400
#define PCNET_TD_MISC_TDR 0x03ff
// Initialization Buffer
#define PCNET_IB_MODE 0
#define PCNET_IB_PADR0 2
#define PCNET_IB_PADR1 4
#define PCNET_IB_PADR2 6
#define PCNET_IB_LADRF0 8
#define PCNET_IB_LADRF1 10
#define PCNET_IB_LADRF2 12
#define PCNET_IB_LADRF3 14
#define PCNET_IB_RDRA 16
#define PCNET_IB_TDRA 20
#define PCNET_IB_SIZE 24
#define PCNET_IB_TDRA_CNT_shift 29
#define PCNET_IB_TDRA_PTR_mask 0x00ffffff
#define PCNET_IB_RDRA_CNT_shift 29
#define PCNET_IB_RDRA_PTR_mask 0x00ffffff
// ------------------------------------------------------------------------
#ifdef KEEP_STATISTICS
struct amd_pcnet_stats {
unsigned int tx_good ;
unsigned int tx_max_collisions ;
unsigned int tx_late_collisions ;
unsigned int tx_underrun ;
unsigned int tx_carrier_loss ;
unsigned int tx_deferred ;
unsigned int tx_sqetesterrors ;
unsigned int tx_single_collisions;
unsigned int tx_mult_collisions ;
unsigned int tx_total_collisions ;
unsigned int rx_good ;
unsigned int rx_crc_errors ;
unsigned int rx_align_errors ;
unsigned int rx_resource_errors ;
unsigned int rx_overrun_errors ;
unsigned int rx_collisions ;
unsigned int rx_short_frames ;
unsigned int rx_too_long_frames ;
unsigned int rx_symbol_errors ;
unsigned int interrupts ;
unsigned int rx_count ;
unsigned int rx_deliver ;
unsigned int rx_resource ;
unsigned int rx_restart ;
unsigned int tx_count ;
unsigned int tx_complete ;
unsigned int tx_dropped ;
};
#endif
typedef struct pcnet_priv_data {
int index;
cyg_uint8 // (split up for atomic byte access)
found:1, // was hardware discovered?
mac_addr_ok:1, // can we bring up?
active:1, // has this if been brung up?
hardwired_esa:1, // set if ESA is hardwired via CDL
txbusy:1, // A packet has been sent
spare1:3;
unsigned long txkey; // Used to ack when packet sent
unsigned char* base; // Base address of controller EPROM region
int interrupt; // Interrupt vector used by controller
unsigned char esa[6]; // Controller ESA
// Function to configure the ESA - may fetch ESA from EPROM or
// RedBoot config option.
void (*config_esa)(struct pcnet_priv_data* cpd);
void *ndp; // Network Device Pointer
cyg_handle_t interrupt_handle;
cyg_interrupt interrupt_object;
int devid;
cyg_uint8* rx_buffers; // ptr to base of buffer mem
cyg_uint8* rx_ring; // ptr to base of rx ring memory
int rx_ring_cnt; // number of entries in ring
int rx_ring_log_cnt; // log of above
int rx_ring_next; // index of next full ring entry
cyg_uint8* tx_buffers;
cyg_uint8* tx_ring;
int tx_ring_cnt;
int tx_ring_log_cnt;
int tx_ring_free; // index of next free ring entry
int tx_ring_alloc; // index of first controller owned ring
int tx_ring_owned; // number of controller owned ring entries
int rxpacket;
#ifdef KEEP_STATISTICS
struct amd_pcnet_stats stats;
#endif
#if DEBUG & 1
cyg_uint32 txd;
#endif
} pcnet_priv_data;
// ------------------------------------------------------------------------
static __inline__ cyg_uint16
get_reg(struct eth_drv_sc *sc, int regno)
{
struct pcnet_priv_data *cpd =
(struct pcnet_priv_data *)sc->driver_private;
cyg_uint16 val, addr;
if (regno & PCNET_ANR_FLAG) {
// We could do this with recursive calls to get/put reg
// functions, but might as well just do it directly.
// First set ANR address
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_RAP, PCNET_BCR_MIIADDR & PCNET_RAP_MASK);
HAL_PCI_IO_READ_UINT16(cpd->base+PCNET_IO_BDP, addr);
addr &= PCNET_BCR_MIIADDR_PHYAD;
addr |= (regno & PCNET_RAP_MASK);
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_BDP, addr);
// Then read ANR register data
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_RAP, PCNET_BCR_MIIDATA & PCNET_RAP_MASK);
HAL_PCI_IO_READ_UINT16(cpd->base+PCNET_IO_BDP, val);
} else {
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_RAP, regno & PCNET_RAP_MASK);
if (regno & PCNET_BCR_FLAG)
HAL_PCI_IO_READ_UINT16(cpd->base+PCNET_IO_BDP, val);
else
HAL_PCI_IO_READ_UINT16(cpd->base+PCNET_IO_RDP, val);
}
#if DEBUG & 2
os_printf("read %s reg %d val 0x%04x\n",
(regno & PCNET_ANR_FLAG) ? "anr" : (regno & PCNET_BCR_FLAG) ? "bcr" : "csr",
regno & PCNET_RAP_MASK, val);
#endif
return val;
}
static __inline__ void
put_reg(struct eth_drv_sc *sc, int regno, cyg_uint16 val)
{
struct pcnet_priv_data *cpd =
(struct pcnet_priv_data *)sc->driver_private;
cyg_uint16 addr;
if (regno & PCNET_ANR_FLAG) {
// We could do this with recursive calls to get/put reg
// functions, but might as well just do it directly.
// First set ANR address
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_RAP, PCNET_BCR_MIIADDR & PCNET_RAP_MASK);
HAL_PCI_IO_READ_UINT16(cpd->base+PCNET_IO_BDP, addr);
addr &= PCNET_BCR_MIIADDR_PHYAD;
addr |= (regno & PCNET_RAP_MASK);
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_BDP, addr);
// Then write ANR register data
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_RAP, PCNET_BCR_MIIDATA & PCNET_RAP_MASK);
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_BDP, val);
} else {
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_RAP, regno & PCNET_RAP_MASK);
if (regno & PCNET_BCR_FLAG)
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_BDP, val);
else
HAL_PCI_IO_WRITE_UINT16(cpd->base+PCNET_IO_RDP, val);
}
#if DEBUG & 2
os_printf("write %s reg %d val 0x%04x\n",
(regno & PCNET_ANR_FLAG) ? "anr" : (regno & PCNET_BCR_FLAG) ? "bcr" : "csr",
regno & PCNET_RAP_MASK, val);
#endif
}
// ------------------------------------------------------------------------
#endif // CYGONCE_DEVS_ETH_AMD_PCNET_H
// EOF amd_pcnet.h
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