upd985xx_eth.h
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#ifndef CYGONCE_HAL_UPD985XX_ETH_H
#define CYGONCE_HAL_UPD985XX_ETH_H
//==========================================================================
//
// upd985xx_eth.h
//
// Architecture specific abstractions for the on-chip ethernet
//
//==========================================================================
//####ECOSGPLCOPYRIGHTBEGIN####
// -------------------------------------------
// This file is part of eCos, the Embedded Configurable Operating System.
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
//
// eCos is free software; you can redistribute it and/or modify it under
// the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 or (at your option) any later version.
//
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with eCos; if not, write to the Free Software Foundation, Inc.,
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
//
// As a special exception, if other files instantiate templates or use macros
// or inline functions from this file, or you compile this file and link it
// with other works to produce a work based on this file, this file does not
// by itself cause the resulting work to be covered by the GNU General Public
// License. However the source code for this file must still be made available
// in accordance with section (3) of the GNU General Public License.
//
// This exception does not invalidate any other reasons why a work based on
// this file might be covered by the GNU General Public License.
//
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
// at http://sources.redhat.com/ecos/ecos-license/
// -------------------------------------------
//####ECOSGPLCOPYRIGHTEND####
//==========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s): hmt, nickg
// Contributors: nickg
// Date: 2001-06-28
// Purpose: Define architecture abstractions
// Description: This file contains any extra or modified definitions for
// this variant of the architecture's ethernet controller.
// Usage: #include <cyg/io/upd985xx_eth.h>
//
//####DESCRIPTIONEND####
//
//==========================================================================
#include <cyg/hal/var_arch.h>
// --------------------------------------------------------------------------
// By default we use the definition of UPD985XX_SYSETH_REG( n ) from
// var_arch.h - if we port to a KORVA with multiple ethernet controllers we
// will have to vary this to account for the different base addresses.
// (the noise at the end of these lines is the default value)
//
// Table 5-2. MAC Control Register Map
//
#define ETH_MACC1 UPD985XX_SYSETH_REG( 0x000) // MAC configuration register 1 R/W 0000_0000H
#define ETH_MACC2 UPD985XX_SYSETH_REG( 0x004) // MAC configuration register 2 R/W 0000_0000H
#define ETH_IPGT UPD985XX_SYSETH_REG( 0x008) // Back-to-Back IPG register R/W 0000_0013H
#define ETH_IPGR UPD985XX_SYSETH_REG( 0x00C) // Non Back-to-Back IPG register R/W 0000_0E13H
#define ETH_CLRT UPD985XX_SYSETH_REG( 0x010) // Collision register R/W 0000_370FH
#define ETH_LMAX UPD985XX_SYSETH_REG( 0x014) // Max packet length register R/W 0000_0600H
// N/A UPD985XX_SYSETH_REG( 0x018) // Reserved for future use - -
#define ETH_RETX UPD985XX_SYSETH_REG( 0x020) // Retry count register R/W 0000_0000H
// N/A UPD985XX_SYSETH_REG( 0x024) // Reserved for future use - -
#define ETH_LSA2 UPD985XX_SYSETH_REG( 0x054) // Station Address register 2 R/W 0000_0000H
#define ETH_LSA1 UPD985XX_SYSETH_REG( 0x058) // Station Address register 1 R/W 0000_0000H
#define ETH_PTVR UPD985XX_SYSETH_REG( 0x05C) // Pause timer value read register R 0000_0000H
// N/A UPD985XX_SYSETH_REG( 0x060) // Reserved for future use - -
#define ETH_VLTP UPD985XX_SYSETH_REG( 0x064) // VLAN type register R/W 0000_0000H
#define ETH_MIIC UPD985XX_SYSETH_REG( 0x080) // MII configuration register R/W 0000_0000H
// N/A UPD985XX_SYSETH_REG( 0x084) // Reserved for future use - -
#define ETH_MCMD UPD985XX_SYSETH_REG( 0x094) // MII command register W 0000_0000H
#define ETH_MADR UPD985XX_SYSETH_REG( 0x098) // MII address register R/W 0000_0000H
#define ETH_MWTD UPD985XX_SYSETH_REG( 0x09C) // MII write data register R/W 0000_0000H
#define ETH_MRDD UPD985XX_SYSETH_REG( 0x0A0) // MII read data register R 0000_0000H
#define ETH_MIND UPD985XX_SYSETH_REG( 0x0A4) // MII indicator register R 0000_0000H
// N/A UPD985XX_SYSETH_REG( 0x0A8) // Reserved for future use - -
#define ETH_AFR UPD985XX_SYSETH_REG( 0x0C8) // Address Filtering register R/W 0000_0000H
#define ETH_HT1 UPD985XX_SYSETH_REG( 0x0CC) // Hash table register 1 R/W 0000_0000H
#define ETH_HT2 UPD985XX_SYSETH_REG( 0x0D0) // Hash table register 2 R/W 0000_0000H
// N/A UPD985XX_SYSETH_REG( 0x0D4) // Reserved for future use - -
#define ETH_CAR1 UPD985XX_SYSETH_REG( 0x0DC) // Carry register 1 R/W 0000_0000H
#define ETH_CAR2 UPD985XX_SYSETH_REG( 0x0E0) // Carry register 2 R/W 0000_0000H
// N/A UPD985XX_SYSETH_REG( 0x0E4) // Reserved for future use - -
#define ETH_CAM1 UPD985XX_SYSETH_REG( 0x130) // Carry mask register 1 R/W 0000_0000H
#define ETH_CAM2 UPD985XX_SYSETH_REG( 0x134) // Carry mask register 2 R/W 0000_0000H
// N/A UPD985XX_SYSETH_REG( 0x138) // Reserved for future use - -
//
// Table 5-3. Statistics Counter Register Map
//
#define ETH_RBYT UPD985XX_SYSETH_REG( 0x140) // Receive Byte Counter R/W
#define ETH_RPKT UPD985XX_SYSETH_REG( 0x144) // Receive Packet Counter R/W
#define ETH_RFCS UPD985XX_SYSETH_REG( 0x148) // Receive FCS Error Counter R/W
#define ETH_RMCA UPD985XX_SYSETH_REG( 0x14C) // Receive Multicast Packet Counter R/W
#define ETH_RBCA UPD985XX_SYSETH_REG( 0x150) // Receive Broadcast Packet Counter R/W
#define ETH_RXCF UPD985XX_SYSETH_REG( 0x154) // Receive Control Frame Packet Counter R/W
#define ETH_RXPF UPD985XX_SYSETH_REG( 0x158) // Receive PAUSE Frame Packet Counter R/W
#define ETH_RXUO UPD985XX_SYSETH_REG( 0x15C) // Receive Unknown OP code Counter R/W
#define ETH_RALN UPD985XX_SYSETH_REG( 0x160) // Receive Alignment Error Counter R/W
#define ETH_RFLR UPD985XX_SYSETH_REG( 0x164) // Receive Frame Length Out of Range Counter R/W
#define ETH_RCDE UPD985XX_SYSETH_REG( 0x168) // Receive Code Error Counter R/W
#define ETH_RFCR UPD985XX_SYSETH_REG( 0x16C) // Receive False Carrier Counter R/W
#define ETH_RUND UPD985XX_SYSETH_REG( 0x170) // Receive Undersize Packet Counter R/W
#define ETH_ROVR UPD985XX_SYSETH_REG( 0x174) // Receive Oversize Packet Counter R/W
#define ETH_RFRG UPD985XX_SYSETH_REG( 0x178) // Receive Error Undersize Packet Counter R/W
#define ETH_RJBR UPD985XX_SYSETH_REG( 0x17C) // Receive Error Oversize Packet Counter R/W
#define ETH_R64 UPD985XX_SYSETH_REG( 0x180) // Receive 64 Byte Frame Counter R/W
#define ETH_R127 UPD985XX_SYSETH_REG( 0x184) // Receive 65 to 127 Byte Frame Counter R/W
#define ETH_R255 UPD985XX_SYSETH_REG( 0x188) // Receive 128 to 255 Byte Frame Counter R/W
#define ETH_R511 UPD985XX_SYSETH_REG( 0x18C) // Receive 256 to 511 Byte Frame Counter R/W
#define ETH_R1K UPD985XX_SYSETH_REG( 0x190) // Receive 512 to 1023 Byte Frame Counter R/W
#define ETH_RMAX UPD985XX_SYSETH_REG( 0x194) // Receive Over 1023 Byte Frame Counter R/W
#define ETH_RVBT UPD985XX_SYSETH_REG( 0x198) // Receive Valid Byte Counter R/W
#define ETH_TBYT UPD985XX_SYSETH_REG( 0x1C0) // Transmit Byte Counter R/W
#define ETH_TPCT UPD985XX_SYSETH_REG( 0x1C4) // Transmit Packet Counter R/W
#define ETH_TFCS UPD985XX_SYSETH_REG( 0x1C8) // Transmit CRC Error Packet Counter R/W
#define ETH_TMCA UPD985XX_SYSETH_REG( 0x1CC) // Transmit Multicast Packet Counter R/W
#define ETH_TBCA UPD985XX_SYSETH_REG( 0x1D0) // Transmit Broadcast Packet Counter R/W
#define ETH_TUCA UPD985XX_SYSETH_REG( 0x1D4) // Transmit Unicast Packet Counter R/W
#define ETH_TXPF UPD985XX_SYSETH_REG( 0x1D8) // Transmit PAUSE control Frame Counter R/W
#define ETH_TDFR UPD985XX_SYSETH_REG( 0x1DC) // Transmit Single Deferral Packet Counter R/W
#define ETH_TXDF UPD985XX_SYSETH_REG( 0x1E0) // Transmit Excessive Deferral Packet Counter R/W
#define ETH_TSCL UPD985XX_SYSETH_REG( 0x1E4) // Transmit Single Collision Packet Counter R/W
#define ETH_TMCL UPD985XX_SYSETH_REG( 0x1E8) // Transmit Multiple collision Packet Counter R/W
#define ETH_TLCL UPD985XX_SYSETH_REG( 0x1EC) // Transmit Late Collision Packet Counter R/W
#define ETH_TXCL UPD985XX_SYSETH_REG( 0x1F0) // Transmit Excessive Collision Packet Counter R/W
#define ETH_TNCL UPD985XX_SYSETH_REG( 0x1F4) // Transmit Total Collision Counter R/W
#define ETH_TCSE UPD985XX_SYSETH_REG( 0x1F8) // Transmit Carrier Sense Error Counter R/W
#define ETH_TIME UPD985XX_SYSETH_REG( 0x1FC) // Transmit Internal MAC Error Counter R/W
//
// Table 5-4. DMA and FIFO Management Registers Map
//
#define ETH_TXCR UPD985XX_SYSETH_REG( 0x200) // Transmit Configuration Register R/W 0000_0000H
#define ETH_TXFCR UPD985XX_SYSETH_REG( 0x204) // Transmit FIFO Control Register R/W FFFF_40C0H
#define ETH_TXDTR UPD985XX_SYSETH_REG( 0x208) // Transmit Data Register W 0000_0000H
#define ETH_TXSR UPD985XX_SYSETH_REG( 0x20C) // Transmit Status Register R 0000_0000H
// N/A UPD985XX_SYSETH_REG( 0x210) // Reserved for future use - -
#define ETH_TXDPR UPD985XX_SYSETH_REG( 0x214) // Transmit Descriptor Pointer R/W 0000_0000H
#define ETH_RXCR UPD985XX_SYSETH_REG( 0x218) // Receive Configuration Register R/W 0000_0000H
#define ETH_RXFCR UPD985XX_SYSETH_REG( 0x21C) // Receive FIFO Control Register R/W C040_0040H
#define ETH_RXDTR UPD985XX_SYSETH_REG( 0x220) // Receive Data Register R 0000_0000H
#define ETH_RXSR UPD985XX_SYSETH_REG( 0x224) // Receive Status Register R 0000_0000H
// N/A UPD985XX_SYSETH_REG( 0x228) // Reserved for future use - -
#define ETH_RXDPR UPD985XX_SYSETH_REG( 0x22C) // Receive Descriptor Pointer R/W 0000_0000H
#define ETH_RXPDR UPD985XX_SYSETH_REG( 0x230) // Receive Pool Descriptor Register R/W 0000_0000H
//
// Table 5-5. Interrupt and Configuration Registers Map
//
#define ETH_CCR UPD985XX_SYSETH_REG( 0x234) // Configuration Register R/W 0000_0000H
#define ETH_ISR UPD985XX_SYSETH_REG( 0x238) // Interrupt Service Register R 0000_0000H
#define ETH_MSR UPD985XX_SYSETH_REG( 0x23C) // Mask Serves Register R/W 0000_0000H
// --------------------------------------------------------------------------
// Now the fields within all those registers...
//
// Table 5-2. MAC Control Register Map
//
// ETH_MACC1 0x000 MAC configuration register 1 R/W 0000_0000H
#define ETH_MACC1_MACLB (1<<14) // MAC loopback: 0
#define ETH_MACC1_TXFC (1<<11) // Transmit flow control enable: 0
#define ETH_MACC1_RXFC (1<<10) // Receive flow control enable: 0
#define ETH_MACC1_SRXEN (1<< 9) // Receive enable: 0
#define ETH_MACC1_PARF (1<< 8) // Control packet pass: 0
#define ETH_MACC1_PUREP (1<< 7) // Pure preamble: 0
#define ETH_MACC1_FLCHT (1<< 6) // Length field check: 0
#define ETH_MACC1_NOBO (1<< 5) // No Back Off: 0
#define ETH_MACC1_CRCEN (1<< 3) // CRC append enable: 0
#define ETH_MACC1_PADEN (1<< 2) // PAD append enable: 0
#define ETH_MACC1_FDX (1<< 1) // Full duplex enable: 0
#define ETH_MACC1_HUGEN (1<< 0) // Large packet enable: 0
// ETH_MACC2 0x004 MAC configuration register 2 R/W 0000_0000H
#define ETH_MACC2_MCRST (1<<10) // MAC Control Block software reset: 0
#define ETH_MACC2_RFRST (1<< 9) // Receive Function Block software reset: 0
#define ETH_MACC2_TFRST (1<< 8) // Transmit Function Block software reset: 0
#define ETH_MACC2_BPNB (1<< 6) // Back Pressure No Back Off: 0
#define ETH_MACC2_APD (1<< 5) // Auto VLAN PAD: 0
#define ETH_MACC2_VPD (1<< 4) // VLAN PAD mode: 0
// ETH_IPGT 0x008 Back-to-Back IPG register R/W 0000_0013H
// ETH_IPGR 0x00C Non Back-to-Back IPG register R/W 0000_0E13H
// ETH_CLRT 0x010 Collision register R/W 0000_370FH
// ETH_LMAX 0x014 Max packet length register R/W 0000_0600H
// N/A 0x018 Reserved for future use - -
// ETH_RETX 0x020 Retry count register R/W 0000_0000H
// N/A 0x024 Reserved for future use - -
// ETH_LSA2 0x054 Station Address register 2 R/W 0000_0000H
// ETH_LSA1 0x058 Station Address register 1 R/W 0000_0000H
// ETH_PTVR 0x05C Pause timer value read register R 0000_0000H
// N/A 0x060 Reserved for future use - -
// ETH_VLTP 0x064 VLAN type register R/W 0000_0000H
#define ETH_VLTP_VLTP (0x00008100) // magic number from example
// ETH_MIIC 0x080 MII configuration register R/W 0000_0000H
#define ETH_MIIC_MIRST (1<<15) // MII Management Interface Block software reset
#define ETH_MIIC_CLKS (0x0C) // 3:2 CLKS Select frequency range:
#define ETH_MIIC_25 (0x00) // 00: HCLK is equal to 25 MHz
#define ETH_MIIC_33 (0x04) // 01: HCLK is less than or equal to 33 MHz
#define ETH_MIIC_50 (0x08) // 10: HCLK is less than or equal to 50 MHz
#define ETH_MIIC_66 (0x0C) // 11: HCLK is less than or equal to 66 MHz
// ETH_MCMD 0x094 MII command register W 0000_0000H
#define ETH_MCMD_SCANC (1<< 1) // SCAN command: 0
#define ETH_MCMD_RSTAT (1<< 0) // MII management read: 0
// ETH_MADR 0x098 MII address register R/W 0000_0000H
#define ETH_MADR_PHY_ADDR_SHIFT (8)
// ETH_MWTD 0x09C MII write data register R/W 0000_0000H
// ETH_MRDD 0x0A0 MII read data register R 0000_0000H
// ETH_MIND 0x0A4 MII indicator register R 0000_0000H
#define ETH_MIND_NVALID (1<< 2) // SCAN command start status: 0
#define ETH_MIND_SCANA (1<< 1) // SCAN command active: 0
#define ETH_MIND_BUSY (1<< 0) // BUSY: 0
// ETH_AFR 0x0C8 Address Filtering register R/W 0000_0000H
#define ETH_AFR_PRO (1<< 3) // Promiscuous mode: 0
#define ETH_AFR_PRM (1<< 2) // Accept Multicast: 0
#define ETH_AFR_AMC (1<< 1) // Accept Multicast ( qualified ): 0
#define ETH_AFR_ABC (1<< 0) // Accept Broadcast: 0
// ETH_HT1 0x0CC Hash table register 1 R/W 0000_0000H
// ETH_HT2 0x0D0 Hash table register 2 R/W 0000_0000H
// ETH_CAR1 0x0DC Carry register 1 R/W 0000_0000H
// ETH_CAR2 0x0E0 Carry register 2 R/W 0000_0000H
// ETH_CAM1 0x130 Carry mask register 1 R/W 0000_0000H
// ETH_CAM2 0x134 Carry mask register 2 R/W 0000_0000H
//
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