usbs_at91.c

开放源码实时操作系统源码.

  protocol = req->type & (USB_DEVREQ_TYPE_MASK);
  
  // Set the next transfer direction
  if (dev_to_host) {        
    SET_BITS (pCSR0, AT91_UDP_CSR_DIR);     /* Set IN direction */
  } else {
    CLEAR_BITS (pCSR0, AT91_UDP_CSR_DIR);   /* Set OUT direction */
  }

  if (protocol == USB_DEVREQ_TYPE_STANDARD) {
    handled = true;
    switch (req->request) {
      case USB_DEVREQ_GET_STATUS:
        status = usbs_at91_control_setup_get_status();
        break;
      case USB_DEVREQ_SET_ADDRESS:
        // Most of the hard work is done by the hardware. We just need
        // to send an ACK.
        usbs_at91_control_setup_send_ack();
        status = EP0_LL_SEND_READY;
        break;
      case USB_DEVREQ_SET_FEATURE:     
        status = usbs_at91_control_setup_set_feature();
        break;
      case USB_DEVREQ_CLEAR_FEATURE:
        status = usbs_at91_control_setup_clear_feature();
        break;
      default:
        handled = false;
    }
  }
  if ((protocol != USB_DEVREQ_TYPE_STANDARD) || !handled) {
    // Ask the layer above to process the message
    usbcode = usbs_parse_host_get_command (&usbs_at91_ep0);
    usbs_at91_ep0.buffer_size = MIN (usbs_at91_ep0.buffer_size, length);
      
    *ppbegin = usbs_at91_ep0.buffer;
    *ppend = *ppbegin + usbs_at91_ep0.buffer_size; /* Ready to send... */
    
    if (usbcode == USBS_CONTROL_RETURN_HANDLED) { /* OK */
      if (dev_to_host) {  
        status = EP0_LL_SEND_READY;
      } else {
        status = EP0_LL_RECEIVE_READY;
      }
    } else {
      status = EP0_LL_STALL;
    }
  }
  // Clear the setup bit so indicating we have processed the message
  CLEAR_BITS (pCSR0, AT91_UDP_CSR_RXSETUP);   
  
  return status;
}

static ep0_low_level_status_t
usbs_at91_control_data_recv(ep0_low_level_status_t status)
{
  cyg_uint32 received = 0;
  cyg_uint32 length;
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[0];
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[0];
  usbs_control_return usbcode;
  
  if (status == EP0_LL_RECEIVE_READY) {
    received = ((*(cyg_uint32 *) pCSR0) >> 16) & 0x7ff;
    length = MIN (received, (cyg_uint32) *ppend - (cyg_uint32) *ppbegin);
    *ppbegin = read_fifo_uint8 (*ppbegin, pFDR0, length);
    
    if (received < usbs_at91_endpoint_fifo_size[0]) {        /* Last packet ? */
      *ppend = *ppbegin;
    }
    
    if (*ppbegin == *ppend) {   /* All received ? */
      usbs_at91_ep0.buffer_size =
        (cyg_uint32) *ppend - (cyg_uint32) usbs_at91_ep0.buffer;
      usbcode = USBS_CONTROL_RETURN_STALL;
      
      if (usbs_at91_ep0.complete_fn) {
        usbcode = (*usbs_at91_ep0.complete_fn) (&usbs_at91_ep0, 0);
      }
      
      if (usbcode == USBS_CONTROL_RETURN_HANDLED) {
        status = EP0_LL_SEND_READY;
      } else {
        status = EP0_LL_STALL;
      }
    }
  }
  
  CLEAR_BITS (pCSR0, AT91_UDP_CSR_RX_DATA_BK0);
  
  return status;
}

static ep0_low_level_status_t
usbs_at91_control_data_sent(ep0_low_level_status_t status)
{
  cyg_uint8 **ppbegin = &usbs_at91_endpoint_pbegin[0];
  cyg_uint8 **ppend = &usbs_at91_endpoint_pend[0];
  cyg_uint32 bytes_to_write = 0;
  usb_devreq *req = (usb_devreq *)usbs_at91_ep0.control_buffer;
  cyg_uint16 value;

  switch (status) {
    case EP0_LL_SEND_READY: 
      if (*ppbegin == *ppend &&
          usbs_at91_ep0.fill_buffer_fn == NULL) {   
        // All bytes are sent, send ACK
        status = EP0_LL_ACK;
        SET_BITS (pCSR0, AT91_UDP_CSR_TXPKTRDY);      // Signal FIFO loaded 
      } else {
        // We have more bytes to send
        bytes_to_write =
          MIN (*ppend - *ppbegin, usbs_at91_endpoint_fifo_size[0]);
        *ppbegin = write_fifo_uint8 (pFDR0, *ppbegin, (cyg_uint8 *) 
                                     ((cyg_uint32) *ppbegin + bytes_to_write));
        // Send next few bytes 
        if (*ppbegin == *ppend) { /* Control-Endoints don't need ACK's */
          if (usbs_at91_ep0.fill_buffer_fn) { // More Records ?
            (*usbs_at91_ep0.fill_buffer_fn) (&usbs_at91_ep0);
            
            *ppbegin = usbs_at91_ep0.buffer;
            *ppend = *ppbegin + usbs_at91_ep0.buffer_size;        
            
            /* Ready to send... */
            bytes_to_write =
              MIN (*ppend - *ppbegin,
                   usbs_at91_endpoint_fifo_size[0] - bytes_to_write);
            
            *ppbegin = write_fifo_uint8 (pFDR0, *ppbegin, (cyg_uint8 *) 
                                         ((cyg_uint32) *ppbegin + bytes_to_write));
            // Send next few bytes 
          } else {
            if (bytes_to_write == usbs_at91_endpoint_fifo_size[0]) {
              // Last packet is full, so we need to send a zero bytes
              // packet next time
              status = EP0_LL_SEND_READY;
            } else {
              status = EP0_LL_IDLE;
            }
            
          }
        }
        SET_BITS (pCSR0, AT91_UDP_CSR_TXPKTRDY);      // Signal FIFO loaded 
      }
      break;
    case EP0_LL_RECEIVE_READY:       
      /* Maybe we have to send an ACK */
      if (*ppbegin == *ppend) {   // All bytes are received, send ACK
        status = EP0_LL_ACK;
        SET_BITS (pCSR0, AT91_UDP_CSR_TXPKTRDY);      // Signal FIFO loaded 
      }
      break;
    case EP0_LL_ACK:
      if (req->request == USB_DEVREQ_SET_ADDRESS) {   // Special-processing 
        HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_FADDR,
                          req->value_lo | AT91_UDP_FADDR_FEN);
        value = (req->value_hi << 8) | req->value_lo;
        if (value) {
          usbs_at91_ep0.state = USBS_STATE_ADDRESSED;
        }
      }
      
      if (usbs_at91_ep0.complete_fn) {
        (*usbs_at91_ep0.complete_fn) (&usbs_at91_ep0,
                                      USBS_CONTROL_RETURN_HANDLED);
      }
      status = EP0_LL_IDLE;
      usbs_state_notify (&usbs_at91_ep0);
      break;
    default:
      break;
  }
  return status;
}
  
static void
usbs_at91_control_dsr (void)
{
  static ep0_low_level_status_t status = EP0_LL_IDLE;
  
  while (!BITS_ARE_CLEARED(pCSR0,
                           AT91_UDP_CSR_TXCOMP | AT91_UDP_CSR_RX_DATA_BK0 |
                           AT91_UDP_CSR_RXSETUP | AT91_UDP_CSR_ISOERROR |
                           AT91_UDP_CSR_RX_DATA_BK1)) {
    
    // Check and handle any error conditions
    if (BITS_ARE_SET (pCSR0, AT91_UDP_CSR_ISOERROR)) {
      status = usbs_at91_control_error(status);
    }
    
    // Check for a setup message and handle it
    if (BITS_ARE_SET (pCSR0, AT91_UDP_CSR_RXSETUP)) {
      status = usbs_at91_control_setup(status);
    }
    
    // Check for received data on the control endpoint
    if (BITS_ARE_SET (pCSR0, AT91_UDP_CSR_RX_DATA_BK0)) {
      status = usbs_at91_control_data_recv(status);
    }
    
    // Check if the last packet has been sent
    if (BITS_ARE_CLEARED (pCSR0, AT91_UDP_CSR_TXPKTRDY)) {
      status = usbs_at91_control_data_sent(status);
    }

    // Received an ACK packet
    if (BITS_ARE_SET (pCSR0, AT91_UDP_CSR_TXCOMP)) {
      CLEAR_BITS (pCSR0, AT91_UDP_CSR_TXCOMP);
    }
    
    if (status == EP0_LL_STALL) {
      CLEAR_BITS (pCSR0, 0x7f);
      SET_BITS (pCSR0, AT91_UDP_CSR_FORCESTALL);
    }
  }
}

static void
usbs_at91_dsr (cyg_vector_t vector, cyg_ucount32 count, cyg_addrword_t data)
{
  cyg_uint8 n;
  
  CYG_ASSERT (CYGNUM_HAL_INTERRUPT_UDP == vector, "Wrong interrupts");
  CYG_ASSERT (0 == data, "DSR needs no data");
  
  CLEAR_BITS (AT91_UDP + AT91_UDP_GLB_STATE, 0x10);

  if (BITS_ARE_SET (pISR, AT91_UDP_WAKEUP)) {
    usbs_at91_ep0.state = USBS_STATE_DEFAULT;
    usbs_state_notify (&usbs_at91_ep0);

    HAL_WRITE_UINT32 (pICR, AT91_UDP_WAKEUP);
  }
  
  if (BITS_ARE_SET (pISR, AT91_UDP_ENDBUSRES)) {        // RESET UDP 
    usbs_at91_ep0.state = USBS_STATE_POWERED;
    usbs_state_notify (&usbs_at91_ep0);
    usbs_at91_handle_reset ();
    
    HAL_WRITE_UINT32 (pCSR0, AT91_UDP_CSR_EPEDS | AT91_UDP_CSR_EPTYPE_CTRL);
    HAL_WRITE_UINT32 (pIER, AT91_UDP_EPINT0);
    
    usbs_at91_ep0.state = USBS_STATE_DEFAULT;
    usbs_state_notify (&usbs_at91_ep0);
    
    HAL_WRITE_UINT32 (pICR, AT91_UDP_ENDBUSRES);
  }

  if (BITS_ARE_SET (pISR, AT91_UDP_SOFINT)) {
    HAL_WRITE_UINT32 (pICR, AT91_UDP_SOFINT);
  }

  if (BITS_ARE_SET (pISR, AT91_UDP_EXTRSM)) {
    usbs_at91_ep0.state = usbs_at91_ep0.state & ~USBS_STATE_SUSPENDED;
    usbs_state_notify (&usbs_at91_ep0);
    HAL_WRITE_UINT32 (pICR, AT91_UDP_EXTRSM);
  }
  
  if (BITS_ARE_SET (pISR, AT91_UDP_RXRSM)) {
    usbs_at91_ep0.state = usbs_at91_ep0.state & ~USBS_STATE_SUSPENDED;
    usbs_state_notify (&usbs_at91_ep0);
    HAL_WRITE_UINT32 (pICR, AT91_UDP_RXRSM);
  }

  if (BITS_ARE_SET (pISR, AT91_UDP_RXSUSP)) {
    usbs_at91_ep0.state = usbs_at91_ep0.state | USBS_STATE_SUSPENDED;
    usbs_state_notify (&usbs_at91_ep0);
    HAL_WRITE_UINT32 (pICR, AT91_UDP_RXSUSP);
  }

  if (BITS_ARE_SET (pISR, AT91_UDP_EPINT0)) {
    usbs_at91_control_dsr ();
  }

  for (n = 1; n < AT91_USB_ENDPOINTS; n++) {
    if (*(cyg_uint32 *) pIMR & (1 << n)) {
      usbs_at91_endpoint_dsr (n);
    }
  }
  
  cyg_drv_interrupt_unmask (vector);
}

static cyg_uint32
usbs_at91_isr (cyg_vector_t vector, cyg_addrword_t data)
{
  cyg_uint8 n;
  bool need_dsr = false;
  cyg_uint32 IMR;
  cyg_uint32 ISR;
  
  CYG_ASSERT (CYGNUM_HAL_INTERRUPT_UDP == vector, "Wrong interrupts");
  CYG_ASSERT (0 == data, "ISR needs no data");

  HAL_READ_UINT32(pIMR, IMR);
  HAL_READ_UINT32(pISR, ISR);
  
  for (n = 1; n < AT91_USB_ENDPOINTS; n++) {    
    /* Do any data endpoint need a data transfer ? */
    if (IMR & ISR & (1 << n)) {
      need_dsr = usbs_at91_endpoint_isr (n) || need_dsr;
    }
  }
  /* If we don't need any DSR re-enable interrupts and finish */
  if (BITS_ARE_CLEARED (pISR, AT91_UDP_ALLOWED_IRQs & 0xffffff01)
      && !need_dsr) {           
    cyg_drv_interrupt_acknowledge (vector);
    return CYG_ISR_HANDLED;
  }

  /* Call the DSR */
  cyg_drv_interrupt_mask (vector);      
  cyg_drv_interrupt_acknowledge (vector);
  
  return CYG_ISR_HANDLED | CYG_ISR_CALL_DSR;
}



// ----------------------------------------------------------------------------
// Polling support. It is not clear that this is going to work particularly
// well since according to the documentation the hardware does not generate
// NAKs automatically - instead the ISR has to set the appropriate bits
// sufficiently quickly to avoid confusing the host.
//
// Calling the isr directly avoids duplicating code, but means that
// cyg_drv_interrupt_acknowledge() will get called when not inside a
// real interrupt handler. This should be harmless.

static void
usbs_at91_poll (usbs_control_endpoint * endpoint)
{
  CYG_ASSERT (endpoint == &usbs_at91_ep0, "Wrong endpoint");
  if (CYG_ISR_CALL_DSR == usbs_at91_isr (CYGNUM_HAL_INTERRUPT_UDP, 0)) {
    usbs_at91_dsr (CYGNUM_HAL_INTERRUPT_UDP, 0, 0);
  }
}

// ----------------------------------------------------------------------------
// Initialization
//
// This routine gets called from a prioritized static constructor during
// eCos startup.

void
usbs_at91_init (void)
{

  cyg_uint32 reg;

  HAL_READ_UINT32 (AT91_PMC + AT91_PMC_PLLR, reg);      
  
  /* Set USB divider so we have a 48MHz clock */
#if   ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED <  48120000) && \
       (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED >  47880000))
  
  // 48MHz clock, divider set to 1
  HAL_WRITE_UINT32 (AT91_PMC + AT91_PMC_PLLR,
                    (reg & 0x0fffffff) | AT91_PMC_PLLR_USBDIV_1);
  
#elif ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED <  96240000) && \
       (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED >  95760000))

  // 96MHz clock, divider set to 2
  HAL_WRITE_UINT32 (AT91_PMC + AT91_PMC_PLLR,
                    (reg & 0x0fffffff) | AT91_PMC_PLLR_USBDIV_2);
#else
#error CYGNUM_HAL_ARM_AT91_CLOCK_SPEED is not 48, 96 or 192MHz plusminus 0.25% ...
#endif

  /* Enable USB clock */
  HAL_WRITE_UINT32 (AT91_PMC + AT91_PMC_SCER, AT91_PMC_SCER_UDP);       
  HAL_WRITE_UINT32 (AT91_PMC + AT91_PMC_PCER, AT91_PMC_PCER_UDP); 

  usbs_at91_set_pullup (false);
#ifndef CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN_NONE
  HAL_ARM_AT91_GPIO_CFG_DIRECTION(CYGDAT_DEVS_USB_AT91_GPIO_SET_PULLUP_PIN,
                                  AT91_PIN_OUT);
#endif
#ifndef CYGDAT_DEVS_USB_AT91_GPIO_READ_POWER_PIN_NONE
  HAL_ARM_AT91_GPIO_CFG_DIRECTION(CYGDAT_DEVS_USB_AT91_GPIO_READ_POWER_PIN,
                                  AT91_PIN_IN);
#endif
  usbs_at91_handle_reset ();
  
  cyg_drv_interrupt_create (CYGNUM_HAL_INTERRUPT_UDP, 
                            6,  // priority
                            0,  // data
                            &usbs_at91_isr,
                            &usbs_at91_dsr,
                            &usbs_at91_intr_handle, &usbs_at91_intr_data);
  
  cyg_drv_interrupt_attach (usbs_at91_intr_handle);
  cyg_drv_interrupt_unmask (CYGNUM_HAL_INTERRUPT_UDP);
  
  HAL_WRITE_UINT32 (AT91_UDP + AT91_UDP_TXVC, 0);
  
  usbs_at91_ep0.state = USBS_STATE_POWERED;
  usbs_state_notify (&usbs_at91_ep0);
}

// ----------------------------------------------------------------------------
// Testing support.
usbs_testing_endpoint usbs_testing_endpoints[] = {
    {
        endpoint_type       : USB_ENDPOINT_DESCRIPTOR_ATTR_CONTROL, 
        endpoint_number     : 0,
        endpoint_direction  : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN,
        endpoint            : (void*) &usbs_at91_ep0,
#ifdef CYGVAR_DEVS_USB_AT91_EP0_DEVTAB_ENTRY
        devtab_entry        : CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "0c",
#else        
        devtab_entry        : (const char*) 0,
#endif        
        min_size            : 1,            // zero-byte control transfers are meaningless
        max_size            : 0x0FFFF,      // limit imposed by protocol
        max_in_padding      : 0,
        alignment           : 0
    },
    {
        endpoint_type       : USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
        endpoint_number     : 1,
        endpoint_direction  : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_OUT,
        endpoint            : (void*) &usbs_at91_ep1,
#ifdef CYGVAR_DEVS_USB_AT91_EP1_DEVTAB_ENTRY
        devtab_entry        : CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "1r",
#else        
        devtab_entry        : (const char*) 0,
#endif        
        min_size            : 1,
        max_size            : -1,           // No hardware or driver limitation
        max_in_padding      : 0,
        alignment           : 0
    },
    {
        endpoint_type       : USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
        endpoint_number     : 2,
        endpoint_direction  : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN,
        endpoint            : (void*) &usbs_at91_ep2,
#ifdef CYGVAR_DEVS_USB_AT91_EP2_DEVTAB_ENTRY
        devtab_entry        : CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "2w",
#else        
        devtab_entry        : (const char*) 0,
#endif        
        min_size            : 1,
        max_size            : -1,           // No hardware or driver limitation
        max_in_padding      : 1,            // hardware limitation
        alignment           : 0
    },
    {
        endpoint_type       : USB_ENDPOINT_DESCRIPTOR_ATTR_BULK,
        endpoint_number     : 3,
        endpoint_direction  : USB_ENDPOINT_DESCRIPTOR_ENDPOINT_IN,
        endpoint            : (void*) &usbs_at91_ep3,
#ifdef CYGVAR_DEVS_USB_AT91_EP3_DEVTAB_ENTRY
        devtab_entry        : CYGDAT_DEVS_USB_AT91_DEVTAB_BASENAME "3w",
#else        
        devtab_entry        : (const char*) 0,
#endif        
        min_size            : 1,
        max_size            : -1,           // No hardware or driver limitation
        max_in_padding      : 1,            // hardware limitation
        alignment           : 0
    },
    USBS_TESTING_ENDPOINTS_TERMINATOR
};