📄 nand.c
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int NF8_ReadPage(U32 block,U32 page,U8 *buffer)
{
U32 i, blockPage;
U32 Mecc, Secc;
U8 *bufPt=buffer;
blockPage=(block<<5)+page;
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command
NF_ADDR(0); // Column = 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & Page num.
NF_ADDR((blockPage>>16)&0xff); //
NF_DETECT_RB();
#if TRANS_MODE==C_LANG
for(i=0;i<512;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
#elif TRANS_MODE==DMA
// Nand to memory dma setting
rSRCPND=BIT_DMA; // Init DMA src pending.
rSUBSRCPND=BIT_SUB_DMA0;
rDISRC0=NFDATA; // Nand flash data register
rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
rDIDST0=(unsigned)bufPt;
rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(512/4/4);
//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSUBSRCPND & BIT_SUB_DMA0)); // Wait until Dma transfer is done.
rSUBSRCPND=BIT_SUB_DMA0;
rSRCPND=BIT_DMA;
#endif
NF_MECC_Lock();
NF_SECC_UnLock();
Mecc=NF_RDDATA();
rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
NF_SECC_Lock();
NF8_Spare_Data[0]=Mecc&0xff;
NF8_Spare_Data[1]=(Mecc&0xff00)>>8;
NF8_Spare_Data[2]=(Mecc&0xff0000)>>16;
NF8_Spare_Data[3]=(Mecc&0xff000000)>>24;
Mecc=NF_RDDATA(); // read 4~7
NF8_Spare_Data[4]=Mecc&0xff;
NF8_Spare_Data[5]=(Mecc&0xff00)>>8;
NF8_Spare_Data[6]=(Mecc&0xff0000)>>16;
NF8_Spare_Data[7]=(Mecc&0xff000000)>>24;
Secc=NF_RDDATA();
rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
NF8_Spare_Data[8]=Secc&0xff;
NF8_Spare_Data[9]=(Secc&0xff00)>>8;
NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
Secc=NF_RDDATA();
NF8_Spare_Data[12]=Secc&0xff;
NF8_Spare_Data[13]=(Secc&0xff00)>>8;
NF8_Spare_Data[14]=(Secc&0xff0000)>>16;
NF8_Spare_Data[15]=(Secc&0xff000000)>>24;
NF_nFCE_H();
if ((rNFECCERR0&0xf) == 0x0){
// printf("ECC OK!\n");
return OK;
}
else {
printf("ECC FAIL!\n");
printf("NFECCERR0: 0x%x\n", rNFECCERR0);
return FAIL;
}
}
///////////////Advanced nand flash //////////////////////
int Adv_NF8_ReadPage(U32 block,U32 page,U8 *buffer)
{
int i;
unsigned int blockPage;
U32 Mecc, Secc;
U8 *bufPt=buffer;
blockPage=(block<<6)+page;
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0x00); // Read command
NF_ADDR(0); // Column (A[7:0]) = 0
NF_ADDR(0); // A[11:8]
NF_ADDR((blockPage)&0xff); // A[19:12]
NF_ADDR((blockPage>>8)&0xff); // A[27:20]
NF_ADDR((blockPage>>16)&0xff); // A[27:20]
NF_CMD(0x30); // 2'nd command
NF_DETECT_RB();
#if TRANS_MODE==C_LANG
for(i=0;i<2048;i++) {
*bufPt++=NF_RDDATA8(); // Read one page
}
#elif TRANS_MODE==DMA
// Nand to memory dma setting
rSRCPND=BIT_DMA; // Init DMA src pending.
rSUBSRCPND=BIT_SUB_DMA0;
rDISRC0=NFDATA; // Nand flash data register
rDISRCC0=(0<<1) | (1<<0); //arc=AHB,src_addr=fix
rDIDST0=(unsigned)bufPt;
rDIDSTC0=(0<<1) | (0<<0); //dst=AHB,dst_addr=inc;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(1<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4/4);
//Handshake,AHB,interrupt,(4-burst),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSUBSRCPND & BIT_SUB_DMA0)); // Wait until Dma transfer is done.
rSUBSRCPND=BIT_SUB_DMA0;
rSRCPND=BIT_DMA;
#endif
NF_MECC_Lock();
NF_SECC_UnLock();
Adv_NF8_Spare_Data[0]=NF_RDDATA8();
Mecc=NF_RDDATA();
rNFMECCD0=((Mecc&0xff00)<<8)|(Mecc&0xff);
rNFMECCD1=((Mecc&0xff000000)>>8)|((Mecc&0xff0000)>>16);
Adv_NF8_Spare_Data[1]=Mecc&0xff;
Adv_NF8_Spare_Data[2]=(Mecc&0xff00)>>8;
Adv_NF8_Spare_Data[3]=(Mecc&0xff0000)>>16;
Adv_NF8_Spare_Data[4]=(Mecc&0xff000000)>>24;
Adv_NF8_Spare_Data[5]=NF_RDDATA8(); // read 5
Adv_NF8_Spare_Data[6]=NF_RDDATA8(); // read 6
Adv_NF8_Spare_Data[7]=NF_RDDATA8(); // read 7
NF_SECC_Lock();
Secc=NF_RDDATA();
rNFSECCD=((Secc&0xff00)<<8)|(Secc&0xff);
Adv_NF8_Spare_Data[8]=Secc&0xff;
Adv_NF8_Spare_Data[9]=(Secc&0xff00)>>8;
Adv_NF8_Spare_Data[10]=(Secc&0xff0000)>>16;
Adv_NF8_Spare_Data[11]=(Secc&0xff000000)>>24;
for(i=12;i<64;i++) {
Adv_NF8_Spare_Data[i]=NF_RDDATA8(); // Read spare array with 4byte width
}
NF_nFCE_H();
if ((rNFECCERR0&0xf) == 0x0){
printf("ECC OK!\n");
return OK;
}
else {
printf("ECC FAIL!\n");
return FAIL;
}
}
int NF8_WritePage(U32 block,U32 page,U8 *buffer)
{
int i;
U32 blockPage, Mecc, Secc;
U8 *bufPt=buffer;
NFConDone=0;
rNFCONT|=(1<<9);
rNFCONT|=(1<<10);
pISR_NFCON= (unsigned)NFCon_Int;
rSRCPND=BIT_NFCON;
rINTMSK=~(BIT_NFCON);
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
blockPage=(block<<5)+page;
NF_nFCE_L();
// NF_CMD(0x0);//??????
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & page num.
NF_ADDR((blockPage>>16)&0xff); //
#if TRANS_MODE==C_LANG
for(i=0;i<512;i++) {
{NF_WRDATA8(*bufPt++);} // Write one page to NFM from buffer
}
#elif TRANS_MODE==DMA
// Memory to Nand dma setting
rSUBSRCPND=BIT_SUB_DMA0;
rSRCPND=BIT_DMA; // Init DMA src pending.
rDISRC0=(unsigned)bufPt; // Nand flash data register
rDISRCC0=(0<<1) | (0<<0); //arc=AHB,src_addr=inc
rDIDST0=NFDATA;
rDIDSTC0=(0<<1) | (1<<0); //dst=AHB,dst_addr=fix;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(0<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(512/4);
// only unit transfer in writing!!!!
//Handshake,AHB,interrupt,(unit),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSUBSRCPND & BIT_SUB_DMA0)); // Wait until Dma transfer is done.
rSUBSRCPND=BIT_SUB_DMA0;
rSRCPND=BIT_DMA;
#endif
NF_MECC_Lock();
// Get ECC data.
// Spare data for 8bit
// byte 0 1 2 3 4 5 6 7 8 9
// ecc [0] [1] [2] [3] x [Bad marking] SECC0 SECC1
Mecc = rNFMECC0;
se8Buf[0]=(U8)(Mecc&0xff);
se8Buf[1]=(U8)((Mecc>>8) & 0xff);
se8Buf[2]=(U8)((Mecc>>16) & 0xff);
se8Buf[3]=(U8)((Mecc>>24) & 0xff);
se8Buf[5]=0xff; // Marking good block
NF_SECC_UnLock();
//Write extra data(ECC, bad marking)
for(i=0;i<4;i++) {
NF_WRDATA8(se8Buf[i]); // Write spare array(Main ECC)
NF8_Spare_Data[i]=se8Buf[i];
}
NF_SECC_Lock();
Secc=rNFSECC;
se8Buf[8]=(U8)(Secc&0xff);
se8Buf[9]=(U8)((Secc>>8) & 0xff);
for(i=4;i<16;i++) {
NF_WRDATA8(se8Buf[i]); // Write spare array(Spare ECC and Mark)
NF8_Spare_Data[i]=se8Buf[i];
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
NF_DETECT_RB();
// while(NFConDone==0);
rNFCONT&=~(1<<9);
rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
if(rNFSTAT&0x20) return FAIL;
NF_CMD(0x70); // Read status command
for(i=0;i<3;i++); //twhr=60ns
if (NF_RDDATA()&0x1) {// Page write error
NF_nFCE_H();
printf("[PROGRAM_ERROR:block#=%d]\n",block);
// NF8_MarkBadBlock(block);
return FAIL;
}
else {
NF_nFCE_H();
return OK;
}
}
//////////////// Advanced nand flash ////////////////////////////////
int Adv_NF8_WritePage(U32 block,U32 page,U8 *buffer)
{
int i;
U32 blockPage, Mecc, Secc;
U8 *bufPt=buffer;
NFConDone=0;
rNFCONT|=(1<<9);
rNFCONT|=(1<<10);
pISR_NFCON= (unsigned)NFCon_Int;
rSRCPND=BIT_NFCON;
rINTMSK=~(BIT_NFCON);
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
blockPage=(block<<6)+page;
NF_nFCE_L();
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column (A[7:0]) = 0
NF_ADDR(0); // A[11:8]
NF_ADDR((blockPage)&0xff); // A[19:12]
NF_ADDR((blockPage>>8)&0xff); // A[27:20]
NF_ADDR((blockPage>>16)&0xff); // A[27:20]
#if TRANS_MODE==C_LANG
for(i=0;i<2048;i++) {
NF_WRDATA8(*bufPt++); // Write one page to NFM from buffer
}
#elif TRANS_MODE==DMA
// Memory to Nand dma setting
rSUBSRCPND=BIT_SUB_DMA0;
rSRCPND=BIT_DMA; // Init DMA src pending.
rDISRC0=(unsigned)bufPt; // Nand flash data register
rDISRCC0=(0<<1) | (0<<0); //arc=AHB,src_addr=inc
rDIDST0=NFDATA;
rDIDSTC0=(0<<1) | (1<<0); //dst=AHB,dst_addr=fix;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(0<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4);
// only unit transfer in writing!!!!
//Handshake,AHB,interrupt,(unit),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSUBSRCPND & BIT_SUB_DMA0)); // Wait until Dma transfer is done.
rSUBSRCPND=BIT_SUB_DMA0;
rSRCPND=BIT_DMA;
#endif
NF_MECC_Lock();
// Get ECC data.
// Spare data for 8bit
// byte 0 1 2 3 4 5 6 7 8 9
// ecc [Bad marking] [0] [1] [2] [3] x SECC0 SECC1
Mecc = rNFMECC0;
Adv_se8Buf[0]=0xff;
Adv_se8Buf[1]=(U8)(Mecc&0xff);
Adv_se8Buf[2]=(U8)((Mecc>>8) & 0xff);
Adv_se8Buf[3]=(U8)((Mecc>>16) & 0xff);
Adv_se8Buf[4]=(U8)((Mecc>>24) & 0xff);
// Marking good block
NF_SECC_UnLock();
//Write extra data(ECC, bad marking)
for(i=0;i<5;i++) {
NF_WRDATA8(Adv_se8Buf[i]); // Write spare array(Main ECC)
Adv_NF8_Spare_Data[i]=Adv_se8Buf[i];
}
NF_SECC_Lock();
Secc=rNFSECC;
Adv_se8Buf[8]=(U8)(Secc&0xff);
Adv_se8Buf[9]=(U8)((Secc>>8) & 0xff);
for(i=5;i<64;i++) {
NF_WRDATA8(Adv_se8Buf[i]); // Write spare array(Spare ECC and Mark)
Adv_NF8_Spare_Data[i]=Adv_se8Buf[i];
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
NF_DETECT_RB();
// while(NFConDone==0);
// rNFCONT&=~(1<<9);
// rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
// if(rNFSTAT&0x20) return FAIL;
NF_CMD(0x70); // Read status command
for(i=0;i<3;i++); //twhr=60ns
if (NF_RDDATA()&0x1) {// Page write error
NF_nFCE_H();
printf("[PROGRAM_ERROR:block#=%d]\n",block);
NF8_MarkBadBlock(block);
return FAIL;
} else {
NF_nFCE_H();
return OK;
}
}
U16 NF8_CheckId(void)
{
int i;
U16 id;
U8 id0, id1, id2, id3;
// rEBICON|=(1<<8);
NF_nFCE_L();
// NF_nCS1_L();
NF_CMD(0x90);
NF_ADDR(0x0);
for (i=0; i<10; i++);
// printf("NFSTAT: 0x%x\n", rNFSTAT);
id0=NF_RDDATA8(); // Maker code 0xec
id1=NF_RDDATA8(); // Devide code(K9S1208V:0x76), (K9K2G16U0M:0xca)
id2=NF_RDDATA8();
id3=NF_RDDATA8();
id=(id0<<8)|(id1);
NF_nFCE_H();
// NF_nCS1_H();
printf("id0:0x%02x, id1:0x%02x,id2:0x%02x,id3:0x%02x \n", id0, id1, id2, id3);
return id;
}
void Nand_Reset(void)
{
int i;
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0xFF); //reset command
for(i=0;i<10;i++); //tWB = 100ns. //??????
NF_DETECT_RB();
NF_nFCE_H();
}
void NF8_Init(void)
{
// for S3C2413
rNFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<0);
// TACLS [14:12] CLE&ALE duration = HCLK*TACLS.
// TWRPH0 [10:8] TWRPH0 duration = HCLK*(TWRPH0+1)
// TWRPH1 [6:4] TWRPH1 duration = HCLK*(TWRPH1+1)
// AdvFlash(R) [3] Advanced NAND, 0:256/512, 1:1024/2048
// PageSize(R) [2] NAND memory page size
// when [3]==0, 0:256, 1:512 bytes/page.
// when [3]==1, 0:1024, 1:2048 bytes/page.
// AddrCycle(R) [1] NAND flash addr size
// when [3]==0, 0:3-addr, 1:4-addr.
// when [3]==1, 0:4-addr, 1:5-addr.
// BusWidth(R/W) [0] NAND bus width. 0:8-bit, 1:16-bit.
//rNFCONT = (0<<17)|(0<<16)|(0<<10)|(0<<9)|(0<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);
rNFCONT = (0<<17)|(0<<16)|(0<<10)|(0<<9)|(0<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(0x3<<1)|(1<<0);
// Lock-tight [17] 0:Disable lock, 1:Enable lock.
// Soft Lock [16] 0:Disable lock, 1:Enable lock.
// EnablillegalAcINT[10] Illegal access interupt control. 0:Disable, 1:Enable
// EnbRnBINT [9] RnB interrupt. 0:Disable, 1:Enable
// RnB_TrandMode[8] RnB transition detection config. 0:Low to High, 1:High to Low
// SpareECCLock [7] 0:Unlock, 1:Lock
// MainECCLock [6] 0:Unlock, 1:Lock
// InitMECC(W) [5] 1:Init main area ECC decoder/encoder.
// InitSECC(W) [4] 1:Init spare area ECC decoder/encoder.
// Reg_nCE1 [2] 0:nFCE=0, 1:nFCE=1.
// Reg_nCE0 [1] 0:nFCE=0, 1:nFCE=1.
// NANDC Enable [0] operating mode. 0:Disable, 1:Enable.
// rNFSTAT = 0;
Nand_Reset();
}
#define SRAM_SADDR 0x40000000
#define SRAM_EADDR (SRAM_SADDR+ (4*1024)) // Total : 4KB, 0x3100_0000-0x3101_FFFF
void SRAM_Test(int Print_msg)
{
U32 addr=0, indata=0, src_data, i;
U32 error;
static int offset=0;
U16 jump_offset=1;
//printf("Check: SRAM Area must be in non-cacheable area!\n");
//printf("SRAM W/R test[%xh-%xh], R/W offset[%d]\n", SRAM_SADDR, SRAM_EADDR-1, offset);
for(i=0; i<3; i++) { // 8/16/32-bit.
// for(i=2; i<3; i++) { // 8/16/32-bit.
if(i==0) jump_offset=1;
else if(i==1) jump_offset=2;
else if(i==2) jump_offset=4;
///////////////////// Clear Source/Target ////////////////////
//printf("Clear data.\n");
for(addr=0; (SRAM_SADDR+addr)<SRAM_EADDR; addr+=4) {
*(U32 *)(SRAM_SADDR+addr) = 0x0;
if(!(addr%(4*1024))) {
//printf("\b\b\b\b\b\b\b\b\b\b%10x", SRAM_SADDR+addr);
}
}
//printf("\b\b\b\b\b\b\b\b\b\b%10x\n", SRAM_SADDR+addr);
///////////////////// Write ////////////////////
//printf("Write data[%x-%x].\n", SRAM_SADDR, SRAM_EADDR);
if(Print_msg>0) printf("Wr(%d-bit)...", jump_offset*8);
if(Print_msg>1) printf("ADDR:%8x", SRAM_SADDR);
Led_Display(0x1);
for(addr=0; (SRAM_SADDR+addr)<SRAM_EADDR; addr+=jump_offset) {
src_data = addr+offset;
switch(jump_offset) {
case 1:
*(U8 *)(SRAM_SADDR+addr) = src_data;
break;
case 2:
*(U16 *)(SRAM_SADDR+addr) = src_data;
break;
case 4:
*(U32 *)(SRAM_SADDR+addr) = src_data;
break;
}
if(!(addr%(4*1024))) {
if(Print_msg>1) printf("\b\b\b\b\b\b\b\b%8x", SRAM_SADDR+addr);
}
}
if(Print_msg>1) printf("\b\b\b\b\b\b\b\b%8x ", SRAM_SADDR+addr);
///////////////////// Verify //////////////////////
//printf("Verify[%x-%x].\n", SRAM_SADDR, SRAM_EADDRs
if(Print_msg>1) printf("ADDR:%8x", SRAM_SADDR);
Led_Display(0x2);
for(error=0, addr=0; (SRAM_SADDR+addr)<SRAM_EADDR; addr+=jump_offset) {
switch(jump_offset) {
case 1:
src_data = (U8)(addr+offset);
indata = *(U8 *)(SRAM_SADDR+addr);
break;
case 2:
src_data = (U16)(addr+offset);
indata = *(U16 *)(SRAM_SADDR+addr);
break;
case 4:
src_data = (U32)(addr+offset);
indata = *(U32 *)(SRAM_SADDR+addr);
break;
}
if(!(addr%(4*1024))) {
if(Print_msg>1) printf("\b\b\b\b\b\b\b\b%8x", SRAM_SADDR+addr);
}
indata = indata|0x800;
if(indata != (src_data|0x800)) {
error++;
printf("%xH[W:%x, R:%x]\n", addr, src_data, indata);
}
}
if(Print_msg>1) printf("\b\b\b\b\b\b\b\b%8x ", SRAM_SADDR+addr);
if(error!=0) {
if(Print_msg>0) printf("ERROR(%d)...\n\n", error);
} else {
if(Print_msg>0) printf("OK!\n");
//printf(".");
}
Led_Display(0xf);
}
offset++;
}
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