📄 dma2.c

📁 三星2443芯片
💻 C
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/*****************************************
  NAME: dma.c
  DESC: DMA memory2memory test
  HISTORY:
  2005.09.15:KIM, KI JUN: draft ver 0.0
 *****************************************/
#include "system.h"
#include "Dma.h" 
#include "Dma2.h" 

typedef struct tagDMA2
{
    volatile U32 DISRC;	    //0x0
    volatile U32 DISRCC;    //0x4
    volatile U32 DIDST;	    //0x8
    volatile U32 DIDSTC;    //0xc
    volatile U32 DCON;	    //0x10
    volatile U32 DSTAT;	    //0x14
    volatile U32 DCSRC;	    //0x18
    volatile U32 DCDST;	    //0x1c
    volatile U32 DMASKTRIG; //0x20
    volatile U32 DMAREQSEL; //0x24
}DMA2;

volatile U32 mSum0[6]={0};
volatile U32 mSum1[6]={0};
volatile U32 dmaEnd[6]={0};
volatile U32 dCnt=0;
volatile U32 DSTAT0_mon0, DCSRC0_mon0, DCDST0_mon0,
		    DSTAT0_mon1, DCSRC0_mon1, DCDST0_mon1;

void M2M0123_Worst(void);
void DMA_M2M_AutoReload(void);
void DMA_M2M_ExtREQ1(void);
void DMA_M2M_ExtREQ2(void);
void DMA_M2M_ExtREQ3(void);
void DMA_M2M_ExtREQ4(void);

void DMA_M2M_ExtREQ_Ctrl(void);
void DMA_M2M_Worst(U32 ch,U32 s_addr, U32 d_addr, U32 tsz, U32 dsz, U32 tot_sz);

static void __irq Dma0End(void);
#if 0
static void __irq Dma1End(void);
static void __irq Dma2End(void);
static void __irq Dma3End(void);
static void __irq Dma4End(void);
static void __irq Dma5End(void);
#endif
static void __irq Dma0AutoReload(void);

void * dma2_func[][2]=
{
	(void *)DMA_M2M_AutoReload,	"M2M Auto-Reload Transfer",
	(void *)DMA_M2M_ExtREQ_Ctrl,"M2M EXT. REQ/ACK Ctrl    ",
	(void *)DMA_M2M_ExtREQ1,	"M2M EXT. Whole/HandShake",
	(void *)DMA_M2M_ExtREQ2,	"M2M EXT. Whole/Demand  ",
	(void *)DMA_M2M_ExtREQ3,	"M2M EXT. Single/HandShake",
	(void *)DMA_M2M_ExtREQ4,	"M2M EXT. Single/Demand  ",
	0,0
};

void Extention_DMA_Test(void)
{
	int i=0;

	while(1)
	{
		i=0;
		printf("\n\n");
		while(1)
		{   //display menu
			printf("%2d:%s",i,dma2_func[i][1]);
			i++;
			if((int)(dma2_func[i][0])==0)
			{
				printf("\n");
				break;
			}
			printf("\n");
		}

		printf("\nPress Enter key to exit : ");
		i = GetIntNum();
		if(i==-1) break;		// return.
		if(i>=0 && (i<((sizeof(dma2_func)-1)/8)) )	// select and execute...
			( (void (*)(void)) (dma2_func[i][0]) )();
	}

}

void DMA_M2M_AutoReload(void)
{
	U32 s_addr;
	U32 d_addr;
	U32 tot_sz;
	U32 tc,tsz;

	pISR_DMA=(int)Dma0AutoReload;
//	pISR_DMA0=(int)Dma0End;

	rINTMSK&=~(BIT_DMA);  
       rINTSUBMSK&=~(BIT_SUB_DMA0);
	   
	tot_sz=0x100000;
	s_addr=_NONCACHE_STARTADDRESS;
	d_addr=_NONCACHE_STARTADDRESS+tot_sz;

	tsz=0;	// Unit Transfer
	tc=tot_sz/((tsz?4:1)*2);	//   case DBYTE :

	dCnt=0;
	dmaEnd[0]=1;
	
	rDISRC0=s_addr;
	rDISRCC0=(0<<1)|(0<<0); // AHB, INC
	rDIDST0=d_addr;
	rDIDSTC0=(0<<1)|(0<<0); // AHB, INC
	rDCON0=(1<<31)|(1<<30)|(1<<29)|(tsz<<28)|(1<<27)|(0<<22)|(1<<20)|(tc);
			   //HS|AHB|InterruptEn|TransferSize|WholeServ|RelaodOn|DByte|TransferCount
	rDMAREQSEL0=0; //S/W request mode
	rDMASKTRIG0=(1<<1)|1; //DMA on, SW_TRIG

	DSTAT0_mon0 = rDSTAT0;
	DCSRC0_mon0 = rDCSRC0;
	DCDST0_mon0 = rDCDST0;

       ///////////////////////////////////////////////////////////////////////////////

	tot_sz=0x100000;
	s_addr=_NONCACHE_STARTADDRESS+0x1000000;
	d_addr=_NONCACHE_STARTADDRESS+0x1000000+tot_sz;

	tsz=0;	// Single Transfer
	tc=tot_sz/((tsz?4:1)*4);	// Data Size Word

	rDISRC0=s_addr;
	rDIDST0=d_addr;
	rDCON0=(1<<31)|(1<<30)|(1<<29)|(tsz<<28)|(1<<27)|(0<<22)|(2<<20)|(tc);

	while(dmaEnd[0]);

       rINTSUBMSK=BIT_SUB_ALLMSK;
	rINTMSK=BIT_ALLMSK;

	printf("Two DMA Done using Auto-Reload option\n");
	printf("[First] src:0x31000000 dst:0x31100000 total size:1MB trans unit:HALF\n");
	printf("DSTAT0 [0x%08x]\n",DSTAT0_mon0);
	printf("DCSRC0 [0x%08x]\n",DCSRC0_mon0);
	printf("DCDST0 [0x%08x]\n",DCDST0_mon0);
	printf("[Second] src:0x32000000 dst:0x32100000 total size:1MB trans unit:WORD\n");
	printf("DSTAT0 [0x%08x]\n",DSTAT0_mon1);
	printf("DCSRC0 [0x%08x]\n",DCSRC0_mon1);
	printf("DCDST0 [0x%08x]\n",DCDST0_mon1);
}

void DMA_M2M_ExtREQ_Ctrl(void)
{
	U32 getkey;
	U32 temp;
	
	// CLKOUT0: OUT, CLKOUT1: IN
	rGPHUDP=rGPHUDP&~(0xf<<26)|(0xa<<26);	// Pull Up Down Disable
	rGPHDAT |= (3<<13);	// GPG0, GPG1 data "1"
	rGPHCON = (rGPHCON&~(0xf<<26))|(0x1<<26);	// GPH13 -> Output,  GPH14 -> Input
	
	printf("nXDREQ nXDACK\n");
	printf("%d %d",(rGPHDAT>>13)&0x1,(rGPHDAT>>14)&0x1);

	while(1) {
		getkey=Uart_getc();
		if(getkey=='t') {
			temp=((rGPHDAT>>13)&0x1);
		    rGPHDAT=rGPHDAT&~(1<<13)|((temp^1)<<13);
		}
		if(getkey=='x') break;
		printf("\b\b\b%d %d",(rGPHDAT>>13)&0x1,(rGPHDAT>>14)&0x1);
		}
}

void DMA_M2M_ExtREQ1(void)
{
	U32 i, temp;
	U32 s_addr;
	U32 d_addr;
	U32 tot_sz;
	U32 tc,tsz;

	rGPBUDP = rGPBUDP & ~(0xf<<14)|(0xa<<14);
	rGPBDAT |= (3<<7);
	rGPBCON = (rGPBCON & ~(0xf<<14))|(0xa<<14);
	rGPBCON = rGPBCON & ~(0x1<<0)|(0x1<<0); // xDACK is active low
	
	pISR_DMA=(int)Dma0End;

    rINTSUBMSK&=~(BIT_SUB_DMA0);
	rINTMSK&=~(BIT_DMA);  

	tot_sz=0x100000;
	s_addr=_NONCACHE_STARTADDRESS;
	d_addr=_NONCACHE_STARTADDRESS+tot_sz;

	tsz=0;	// Unit Transfer
	tc=tot_sz/((tsz?4:1)*2);	//	 case DBYTE :

	dmaEnd[0]=1;
	mSum0[0]=0;
	mSum1[0]=0;
	
	// Destination Memory Clear
	for(i=d_addr;i<(d_addr+tot_sz);i+=4) {
		*((U32 *)i)=0;
		}

	for(i=s_addr;i<(s_addr+tot_sz);i+=4)
	{
			*((U32 *)i)=i^0x55aa5aa5;
			mSum0[0]+=*((U32 *)i);
	}

	rDISRC0=s_addr;
	rDISRCC0=(0<<1)|(0<<0); // AHB, INC
	rDIDST0=d_addr;
	rDIDSTC0=(0<<1)|(0<<0); // AHB, INC
	rDCON0=(1<<31)|(0<<30)|(1<<29)|(tsz<<28)|(1<<27)|(0<<22)|(1<<20)|(tc);
			   //HS|APB|InterruptEn|TransferSize|WholeServ|RelaodOn|DByte|TransferCount
	rDMAREQSEL0=(18<<1)|(1<<0); //nXDREQ0
	rDMASKTRIG0=(1<<1); //DMA on

	printf("Waiting for nXDREQ\n");
	///////////////////////////////////////////////////////////////////////////////

	while(dmaEnd[0]) {
		temp= rDSTAT0&0xfffff;
//		printf("0x%08x\n",(rDSTAT0&0xfffff));
		if(Uart_GetKey()) break;
		if(temp!=(rDSTAT0&0xfffff))
		printf("\b\b\b\b\b\b\b\b%08x",(rDSTAT0&0xfffff));
		}
	printf("M2M Done\n");

     rINTSUBMSK=BIT_SUB_ALLMSK;
	rINTMSK=BIT_ALLMSK;

	for(i=d_addr;i<(d_addr+tot_sz);i+=4)
	{
			mSum1[0]+=*((U32 *)i);
	}

	if(mSum0[0]==mSum1[0])
		printf("[Ch: 0, Size: %d KB] DMA test (Handshake, Whole service) O.K.\n",tot_sz/1024);
	else 
		printf("[Ch: 0, Size: %d KB] DMA test (Handshake, Whole service) ERROR!!!\n",tot_sz/1024);
}

void DMA_M2M_ExtREQ2(void)
{
	U32 i, temp;
	U32 s_addr;
	U32 d_addr;
	U32 tot_sz;
	U32 tc,tsz;

	rGPBUDP = rGPBUDP & ~(0xf<<14)|(0xa<<14);
	rGPBDAT |= (3<<7);
	rGPBCON = (rGPBCON & ~(0xf<<14))|(0xa<<14);
	rGPBCON = rGPBCON & ~(0x1<<0)|(0x1<<0); // xDACK is active low
	
	pISR_DMA=(int)Dma0End;

	rINTSUBMSK&=~(BIT_SUB_DMA0);
	rINTMSK&=~(BIT_DMA);  

	tot_sz=0x100000;
	s_addr=_NONCACHE_STARTADDRESS;
	d_addr=_NONCACHE_STARTADDRESS+tot_sz;

	tsz=0;	// Unit Transfer
	tc=tot_sz/((tsz?4:1)*2);	//	 case DBYTE :

	dmaEnd[0]=1;
	mSum0[0]=0;
	mSum1[0]=0;

	// Destination Memory Clear
	for(i=d_addr;i<(d_addr+tot_sz);i+=4) {
		*((U32 *)i)=0;
		}

	for(i=s_addr;i<(s_addr+tot_sz);i+=4)
	{
			*((U32 *)i)=i^0x55aa5aa5;
			mSum0[0]+=*((U32 *)i);
	}

	rDISRC0=s_addr;
	rDISRCC0=(0<<1)|(0<<0); // AHB, INC
	rDIDST0=d_addr;
	rDIDSTC0=(0<<1)|(0<<0); // AHB, INC
	rDCON0=(0<<31)|(0<<30)|(1<<29)|(tsz<<28)|(1<<27)|(0<<22)|(1<<20)|(tc);
		   //Demand|APB|InterruptEn|TransferSize|WholeServ|RelaodOn|DByte|TransferCount
	rDMAREQSEL0=(18<<1)|(1<<0); //nXDREQ0
	rDMASKTRIG0=(1<<1); //DMA on

	printf("Waiting for nXDREQ\n");
	///////////////////////////////////////////////////////////////////////////////

	while(dmaEnd[0]) {
		temp= rDSTAT0&0xfffff;
//		printf("0x%08x\n",(rDSTAT0&0xfffff));
		if(Uart_GetKey()) break;
		if(temp!=(rDSTAT0&0xfffff))
		printf("\b\b\b\b\b\b\b\b%08x",(rDSTAT0&0xfffff));
		}
	printf("M2M Done\n");
	
       rINTSUBMSK=BIT_SUB_ALLMSK;
	rINTMSK=BIT_ALLMSK;

	for(i=d_addr;i<(d_addr+tot_sz);i+=4)
	{
			mSum1[0]+=*((U32 *)i);
	}

	if(mSum0[0]==mSum1[0])
		printf("[Ch: 0, Size: %d KB] DMA test (Demand, Whole service) O.K.\n",tot_sz/1024);
	else 
		printf("[Ch: 0, Size: %d KB] DMA test (Demand, Whole service) ERROR!!!\n",tot_sz/1024);
}

void DMA_M2M_ExtREQ3(void)
{
	U32 i, temp;
	U32 s_addr;
	U32 d_addr;
	U32 tot_sz;
	U32 tc,tsz;

	rGPBUDP = rGPBUDP & ~(0xf<<14)|(0xa<<14);
	rGPBDAT |= (3<<7);
	rGPBCON = (rGPBCON & ~(0xf<<14))|(0xa<<14);
	rGPBCON = rGPBCON & ~(0x1<<0)|(0x1<<0); // xDACK is active low
	
	pISR_DMA=(int)Dma0End;
	
    rINTSUBMSK&=~(BIT_SUB_DMA0);
	rINTMSK&=~(BIT_DMA);  

	tot_sz=0x10;
	s_addr=_NONCACHE_STARTADDRESS;
	d_addr=_NONCACHE_STARTADDRESS+tot_sz;

	tsz=0;	// Unit Transfer
	tc=tot_sz/((tsz?4:1)*2);	//	 case DBYTE :

	dmaEnd[0]=1;
	mSum0[0]=0;
	mSum1[0]=0;

	// Destination Memory Clear
	for(i=d_addr;i<(d_addr+tot_sz);i+=4)
		*((U32 *)i)=0;

	for(i=s_addr;i<(s_addr+tot_sz);i+=4)
	{
			*((U32 *)i)=i^0x55aa5aa5;
			mSum0[0]+=*((U32 *)i);
	}

	rDISRC0=s_addr;
	rDISRCC0=(0<<1)|(0<<0); // AHB, INC
	rDIDST0=d_addr;
	rDIDSTC0=(0<<1)|(0<<0); // AHB, INC
	rDCON0=(1<<31)|(0<<30)|(1<<29)|(tsz<<28)|(0<<27)|(1<<22)|(1<<20)|(tc);
			   //HS|APB|InterruptEn|TransferSize|SingleServ|RelaodOff|DByte|TransferCount
	rDMAREQSEL0=(18<<1)|(1<<0); //nXDREQ0
	rDMASKTRIG0=(1<<1); //DMA on

	printf("Waiting for nXDREQ\n");
	///////////////////////////////////////////////////////////////////////////////
	printf("Current TC : ");
	printf("%08x",(rDSTAT0&0xfffff));
	while(dmaEnd[0]) {
		temp= rDSTAT0&0xfffff;
//		printf("0x%08x\n",(rDSTAT0&0xfffff));
		if(Uart_GetKey()) break;
		if(temp!=(rDSTAT0&0xfffff))
		printf("\b\b\b\b\b\b\b\b%08x",(rDSTAT0&0xfffff));
		}
	printf("\nM2M Done\n");

	rINTSUBMSK=BIT_SUB_ALLMSK;
	rINTMSK=BIT_ALLMSK;

	for(i=d_addr;i<(d_addr+tot_sz);i+=4)
	{
			mSum1[0]+=*((U32 *)i);
	}

	if(mSum0[0]==mSum1[0])
		printf("[Ch: 0, Size: %d Byte] DMA test (Handshake, Single service) O.K.\n",tot_sz);
	else 
		printf("[Ch: 0, Size: %d Byte] DMA test (Handshake, Single service) ERROR!!!\n",tot_sz);
}

void DMA_M2M_ExtREQ4(void)
{
	U32 i, temp;
	U32 s_addr;
	U32 d_addr;
	U32 tot_sz;
	U32 tc,tsz;

	rGPBUDP = rGPBUDP & ~(0xf<<14)|(0xa<<14);
	rGPBDAT |= (3<<7);
	rGPBCON = (rGPBCON & ~(0xf<<14))|(0xa<<14);
	rGPBCON = rGPBCON & ~(0x1<<0)|(0x1<<0); // xDACK is active low
	
	pISR_DMA=(int)Dma0End;

	rINTSUBMSK&=~(BIT_SUB_DMA0);
	rINTMSK&=~(BIT_DMA);  

	tot_sz=0x10;
	s_addr=_NONCACHE_STARTADDRESS;
	d_addr=_NONCACHE_STARTADDRESS+tot_sz;

	tsz=0;	// Unit Transfer
	tc=tot_sz/((tsz?4:1)*2);	//	 case DBYTE :

	dmaEnd[0]=1;
	mSum0[0]=0;
	mSum1[0]=0;

	// Destination Memory Clear
	for(i=d_addr;i<(d_addr+tot_sz);i+=4)
		*((U32 *)i)=0;

	for(i=s_addr;i<(s_addr+tot_sz);i+=4)
	{
			*((U32 *)i)=i^0x55aa5aa5;
			mSum0[0]+=*((U32 *)i);
	}

	rDISRC0=s_addr;
	rDISRCC0=(0<<1)|(0<<0); // AHB, INC
	rDIDST0=d_addr;
	rDIDSTC0=(0<<1)|(0<<0); // AHB, INC
	rDCON0=(0<<31)|(0<<30)|(1<<29)|(tsz<<28)|(1<<27)|(0<<22)|(1<<20)|(tc);
		   //Demand|APB|InterruptEn|TransferSize|SingleServ|RelaodOn|DByte|TransferCount
	rDMAREQSEL0=(18<<1)|(1<<0); //nXDREQ0
	rDMASKTRIG0=(1<<1); //DMA on

	printf("Waiting for nXDREQ\n");
	///////////////////////////////////////////////////////////////////////////////
	printf("Current TC : ");
	printf("%08x",(rDSTAT0&0xfffff));

	while(dmaEnd[0]) {
		temp= rDSTAT0&0xfffff;
//		printf("0x%08x\n",(rDSTAT0&0xfffff));
		if(Uart_GetKey()) break;
		if(temp!=(rDSTAT0&0xfffff))
		printf("\b\b\b\b\b\b\b\b%08x",(rDSTAT0&0xfffff));
		}
	printf("\nM2M Done\n");

	rINTSUBMSK=BIT_SUB_ALLMSK;
	rINTMSK=BIT_ALLMSK;

	for(i=d_addr;i<(d_addr+tot_sz);i+=4)
	{
			mSum1[0]+=*((U32 *)i);
	}

	if(mSum0[0]==mSum1[0])
		printf("[Ch: 0, Size: %d KB] DMA test (Demand, Single service) O.K.\n",tot_sz/1024);
	else 
		printf("[Ch: 0, Size: %d KB] DMA test (Demand, Single service) ERROR!!!\n",tot_sz/1024);
}

static void __irq Dma0AutoReload(void)
{
    rSUBSRCPND|=BIT_SUB_DMA0;
    ClearPending(BIT_DMA);
    dCnt++;
    if(dCnt>1) dmaEnd[0]=0;
    else {
	rDMASKTRIG0 |= 1;
	DSTAT0_mon1 = rDSTAT0;
	DCSRC0_mon1 = rDCSRC0;
	DCDST0_mon1 = rDCDST0;
    	}
    printf(".");
}

static void __irq Dma0End(void)
{
    rSUBSRCPND|=BIT_SUB_DMA0;
    ClearPending(BIT_DMA);
    dmaEnd[0]=0;
}
#if 0
static void __irq Dma1End(void)
{
     rSUBSRCPND|=BIT_SUB_DMA1;
    ClearPending(BIT_DMA);
    dmaEnd[1]=0;
}

static void __irq Dma2End(void)
{
     rSUBSRCPND|=BIT_SUB_DMA2;
    ClearPending(BIT_DMA);
    dmaEnd[2]=0;
}

static void __irq Dma3End(void)
{
     rSUBSRCPND|=BIT_SUB_DMA3;
    ClearPending(BIT_DMA);
    dmaEnd[3]=0;
}

static void __irq Dma4End(void)
{
     rSUBSRCPND|=BIT_SUB_DMA4;
    ClearPending(BIT_DMA);
    dmaEnd[4]=0;
}

static void __irq Dma5End(void)
{
     rSUBSRCPND|=BIT_SUB_DMA5;
    ClearPending(BIT_DMA);
    dmaEnd[5]=0;
}
#endif
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