mmucache.c

三星2443芯片

/*======================================================================

 Project Name : S3C2443 verification project

 Copyright 2006 by Samsung Electronics, Inc.
 All rights reserved.

 Project Description :
 This software is only for verifying functions of the S3C2443. 
 Anybody can use this code without our permission.

 File Name    : MMUCache.c
 Description  : MMU library (32MB)
 Author       : Junon Jeon
 Dept         : AP
 Created Date : 2006.06.02
 Version      : 0.0
 History
   R0.0 (2006.06.02): Junon draft
		- This code is derived from mmu.c of S3C2440 test code.
		
=======================================================================*/

#include "system.h"

// 1) Only the section table is used. 
// 2) The cachable/non-cachable area can be changed by MMT_DEFAULT value.
//    The section size is 1MB.


void MMU_Init(void)
{
    int i,j;
    //========================== IMPORTANT NOTE =========================
    //The current stack and code area can't be re-mapped in this routine.
    //If you want memory map mapped freely, your own sophiscated MMU
    //initialization code is needed.
    //===================================================================

    // Set async mode in ARM920T
	MMU_SetAsyncBusMode();
	
    //If write-back is used,the DCache should be cleared. Dcache must be enabled.   
    // different point between ARM920T & ARM926EJ
	for(i=0;i<64;i++)
    	for(j=0;j<8;j++) 
    	    MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));

    MMU_DisableDCache();
    MMU_DisableICache();

    MMU_InvalidateICache();

    #if 0
    //To complete MMU_Init() fast, Icache may be turned on here.
    MMU_EnableICache(); 
    #endif

    MMU_DisableMMU();
    MMU_InvalidateTLB();

    /*SROM*/
    //MMU_SetMTT(int vaddrStart,int vaddrEnd,int paddrStart,int attr)
    MMU_SetMTT(0x00000000,0x07f00000,0x00000000,RW_NCNB);   //SROM Bank0
    MMU_SetMTT(0x08000000,0x0ff00000,0x08000000,RW_NCNB);   //SROM Bank1
    MMU_SetMTT(0x10000000,0x17f00000,0x10000000,RW_NCNB);   //SROM Bank2
    MMU_SetMTT(0x18000000,0x1ff00000,0x18000000,RW_NCNB);   //SROM Bank3
    MMU_SetMTT(0x20000000,0x27f00000,0x20000000,RW_NCNB);   //SROM Bank4
    MMU_SetMTT(0x28000000,0x2ff00000,0x28000000,RW_NCNB);   //SROM Bank5
    
    //MMU_SetMTT(0x0c000000,0x0c000000,0x0c000000,RW_NCNB);  //Stepping Stone 4KB

    /*Normal SDRAM*/    
    MMU_SetMTT(0x30000000,0x30f00000,0x30000000,RW_CB);    //BANK6 - SDRAM 
    MMU_SetMTT(0x31000000,0x33e00000,0x31000000,RW_NCNB);  //
    MMU_SetMTT(0x33f00000,0x33f00000,0x33f00000,RW_CB);    //
    MMU_SetMTT(0x38000000,0x3ff00000,0x38000000,RW_NCNB);  //BANK7 - SDRAM

    /*SFR & Etc*/    
    MMU_SetMTT(0x40000000,0x47f00000,0x40000000,RW_NCNB); //SFR
    MMU_SetMTT(0x48000000,0x5af00000,0x48000000,RW_NCNB); //SFR
    MMU_SetMTT(0x5b000000,0x5b000000,0x5b000000,RW_NCNB); //SFR
    MMU_SetMTT(0x5b100000,0xfff00000,0x5b100000,RW_FAULT);//not used

    MMU_SetTTBase(_MMUTT_STARTADDRESS);
    MMU_SetDomain(0x55555550|DOMAIN1_ATTR|DOMAIN0_ATTR); 
    	//DOMAIN1: no_access, DOMAIN0,2~15=client(AP is checked)

    MMU_SetProcessId(0x0);
    MMU_EnableAlignFault();

    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache(); //DCache should be turned on after MMU is turned on.    
}    


void MMU_SetMTT(unsigned int vaddrStart,unsigned int vaddrEnd,unsigned int paddrStart,unsigned int attr)
{
    unsigned int *pTT;
    unsigned int i,nSec;
    
    pTT=(unsigned int *)_MMUTT_STARTADDRESS+(vaddrStart>>20);
    nSec=(vaddrEnd>>20)-(vaddrStart>>20);
    
    for(i=0;i<=nSec;i++)*pTT++=attr |(((paddrStart>>20)+i)<<20);
}


// attr=RW_CB,RW_CNB,RW_NCNB,RW_FAULT
void ChangeRomCacheStatus(int attr)
{
    int i,j;
    
    MMU_DisableDCache();
    MMU_DisableICache();
    
    //If write-back is used,the DCache should be cleared.
    // different point between ARM920T & ARM926EJ
    for(i=0;i<64;i++) 
    	for(j=0;j<8;j++)
    	    MMU_CleanInvalidateDCacheIndex((i<<26)|(j<<5));
    MMU_InvalidateICache();
    MMU_DisableMMU();
    MMU_InvalidateTLB();

    MMU_SetMTT(0x00000000,0x03f00000,0x00000000,attr);  //SROM Bank0
    MMU_SetMTT(0x08000000,0x0bf00000,0x08000000,attr);  //SROM Bank1

    MMU_EnableMMU();
    MMU_EnableICache();
    MMU_EnableDCache();
}