s3c2410.h

混泰CH7023,CH7024,CH7025视频解码芯片

#ifndef _S3C2410_H_
#define _S3C2410_H_

/***************************************************************************************

	FileName: 		S3C2410.H

	CPU:  			Samsung 2410

	System:			WinCE 4.2

	Description:	This file declears some structures and functions for using CH7025.
	
	Author:   		JUNFENG WANG

	Create Date:	2007-5-11
	
	Modify:			2007-6-25 By JUNFENG WANG

*****************************************************************************************/

#define DEBUG_ZONE	1

//redefine register structs (from s2410.h):
#define S3C2410_IOP_PA_BASE		(0x56000000)
#define S3C2410_IOP_VA_BASE		(0xB1600000) // 0x56000000
typedef struct  {
    unsigned int  rGPACON;		// 00
    unsigned int  rGPADAT;
    unsigned int  rPAD1[2];
    
    unsigned int  rGPBCON;		// 10
    unsigned int  rGPBDAT;
    unsigned int  rGPBUP;
    unsigned int  rPAD2;
    
    unsigned int  rGPCCON;		// 20
    unsigned int  rGPCDAT;
    unsigned int  rGPCUP;
    unsigned int  rPAD3;
    
    unsigned int  rGPDCON;		// 30
    unsigned int  rGPDDAT;
    unsigned int  rGPDUP; 
    unsigned int  rPAD4;
    
    unsigned int  rGPECON;		// 40
    unsigned int  rGPEDAT;
    unsigned int  rGPEUP;
    unsigned int  rPAD5;
    
    unsigned int  rGPFCON;		// 50
    unsigned int  rGPFDAT;
    unsigned int  rGPFUP; 
    unsigned int  rPAD6;
    
    unsigned int  rGPGCON;		// 60
    unsigned int  rGPGDAT;
    unsigned int  rGPGUP; 
    unsigned int  rPAD7;
    
    unsigned int  rGPHCON;		// 70
    unsigned int  rGPHDAT;
    unsigned int  rGPHUP; 
    unsigned int  rPAD8;
    
    unsigned int  rMISCCR;		// 80
    unsigned int  rDCKCON;		
    unsigned int  rEXTINT0;
    unsigned int  rEXTINT1;		
    unsigned int  rEXTINT2;		// 90
	unsigned int  rEINTFLT0;
	unsigned int  rEINTFLT1;
	unsigned int  rEINTFLT2;
	unsigned int  rEINTFLT3;		// A0
	unsigned int  rEINTMASK;
	unsigned int  rEINTPEND;
	unsigned int  rGSTATUS0;		// AC
	unsigned int  rGSTATUS1;		// B0
	unsigned int  rGSTATUS2;		// B4
	unsigned int  rGSTATUS3;		// B8
	unsigned int  rGSTATUS4;		// BC
	
}S3C2410_IOPreg;

#define S3C2410_LCD_PA_BASE		(0x4D000000)
#define S3C2410_LCD_VA_BASE		(0xB0D00000) // 0x4D000000
typedef struct  {
    unsigned int  rLCDCON1;		// 00
    unsigned int  rLCDCON2;		// 04
    unsigned int  rLCDCON3;		// 08
    unsigned int  rLCDCON4;		// 0C
    unsigned int  rLCDCON5;		// 10
    unsigned int  rLCDSADDR1;	// 14
    unsigned int  rLCDSADDR2;	// 18
    unsigned int  rLCDSADDR3;	// 1C
    unsigned int  rREDLUT;		// 20
    unsigned int  rGREENLUT;	// 24
    unsigned int  rBLUELUT;		// 28
    unsigned int  rPAD[8];		// 2C - 48
    unsigned int  rDITHMODE;	// 4C
    unsigned int  rTPAL;		// 50
    unsigned int  rLCDINTPND;	// 54
    unsigned int  rLCDSRCPND;	// 58
    unsigned int  rLCDINTMSK;	// 5C	
    unsigned int  rLPCSEL;		// 60
}S3C2410_LCDreg;    

#define S3C2410_IIC_PA_BASE			0x54000000	
#define S3C2410_IIC_VA_BASE			0xB1400000 // 54000000
typedef struct{
        unsigned int    rIICCON;
        unsigned int    rIICSTAT;
        unsigned int    rIICADD;
        unsigned int    rIICDS;
}S3C2410_IICreg;        

#define S3C2410_UART_PA_BASE				0x50000000
#define S3C2410_UART0_VA_BASE			    0xB1000000 
#define S3C2410_UART1_VA_BASE			    0xB1004000
#define S3C2410_UART2_VA_BASE				0xB1008000
typedef struct  {
    unsigned int  rULCON;
    unsigned int  rUCON;
    unsigned int  rUFCON;
    unsigned int  rUMCON;
    unsigned int  rUTRSTAT;
    unsigned int  rUERSTAT;
    unsigned int  rUFSTAT;
    unsigned int  rUMSTAT;
    unsigned int  rUTXH;
    unsigned int  rURXH;
    unsigned int  rUBRDIV;
}S3C2410_UART0reg, S3C2410_UART1reg, S3C2410_UART2reg, S3C2410_UARTreg, S3C2410_S2410_UART_REG, *PS3C2410_S2410_UART_REG;

#define FRAMEBUF_SIZE					0x30000   // 640x480x(bpp/8)=0x96000 320x240x2=0x25800

//-------------------------------------
// Definition for escape code
//-------------------------------------
#define OEMES_CODEBASE				100000
#define DRVESC_JUSTTEST				(OEMES_CODEBASE+1)
#define DRVESC_CHANGELCDTIMING		(OEMES_CODEBASE+100)
#define DRVESC_GETLCDTIMING			(OEMES_CODEBASE+200)  

#define DRVESC_CHIPI2CREAD			(OEMES_CODEBASE+101)
#define DRVESC_CHIPI2CWRITE			(OEMES_CODEBASE+102)
//for IIC module
#define DRVESC_IICCHANGEADDR		(OEMES_CODEBASE+103)
#define DRVESC_IICINIT				(OEMES_CODEBASE+104)
#define DRVESC_IICREAD				(OEMES_CODEBASE+105)
#define DRVESC_IICWRITE				(OEMES_CODEBASE+106)
#define DRVESC_IICTEST				(OEMES_CODEBASE+107)
#define DRVESC_UARTTEST				(OEMES_CODEBASE+108)

#define DRVESC_CHIPRESET			(OEMES_CODEBASE+109)

//for chrontel chip
#define DRVESC_SETUP7023			(OEMES_CODEBASE+110)

#define CH7025_ADDR					0xEC 

typedef struct{
	UINT clkdiv;
	UINT ha;
	UINT hfp;
	UINT hbp;
	UINT hw;
	UINT va;
	UINT vfp;
	UINT vbp;
	UINT vw;
}TIMING,*PTIMING;

typedef enum{
	CHIP_CH7026=0,
	CHIP_CH7025,
	CHIP_NUMBER,
}CHIP_TYPE;
	

//Functions declare:
CHIP_TYPE FindChrontelChip();

void InitChrontelChip(CHIP_TYPE chiptype);

//For CH7023:
void CH7023Init();

//For CH7025:
void CH7025Init();

//assistant functions:
void  CheckLCDReg();

#endif //S3C2410_WANG_H_