t101_util.c

宏芯T102芯片驱动（51单片机作主控）

#include <reg51.h>
#include "math.h"
#include "common.h"
#include "system.h"
#include "struct.h"
#include "T101_Util.h"
#include "TW101Reg.h"
#include "twowire.h"
#include "display.h"
#include "keypad.h"
#include "T515.h" 



extern uCHAR idata m_cStandard;
extern uCHAR idata m_cScaleratio;
extern uWORD m_wHRes;
extern uWORD m_wVRes;
extern uWORD idata m_wBuff[3];
extern uCHAR IDATA m_cBuff[4];
extern uWORD m_wDWHSZ;
extern uWORD idata m_wVTotal;
//extern uCHAR cSVideo;
extern uCHAR idata m_cSource;
extern uCHAR idata m_cCurreKey;
extern bit AdjustSig;
uCHAR NoSignal=0;

static uCHAR cSVideo=0;


#ifdef NEW_BOARD
unsigned int uiaSrcMux[]={
0x0000,
0x0a00,//0x0404,//0x0804,//CVBS1
0x0804,
0x0004, // SVIDOE1
0x0504, 
0x0004,
}; // set the input mux values here, P0_18, P0_19

#else
unsigned int uiaSrcMux[]={
0x0000,
0x0100,
0x0000,  //CVBS2
0x0804,
0x200C,
0x0007,}; // set the input mux values here, P0_18, P0_19
#endif


//Ruby add 2004-06-21
#ifdef ROTATE
    uCHAR Dis_Mode=TOP_LEFT;
#endif


#ifdef TCON
#define TCON_index   0x20
unsigned char i=0;

#ifdef A35_VGA
unsigned char TCON_data[]={  //20~35
0x23,0x7d,0xB0,0x00,//0x21,0x7d,0xB0,0x00,
0x03,0xb0,0x00,0xae,
0x00,0x1c,0x00,0x01,
0x18,0x03,0x00,0x00,
0x01,0xa4,0x00,0x0c,
0x00,0x06};


unsigned char Output_timing[]={  //B0~BF
0x10,0x00,0x0d,0x00,
0xA0,0x00,0xEA,0x00,
0xCE,0x00,0x06,0x01,
0x10,0x00,0x03,0x00
};

 unsigned char Timing_index=0xB0;
#endif

#ifdef PVI_35
unsigned char TCON_data[]={  //20~35
0x21,0x78,0x60,0x01,
0x06,0x60,0x01,0x5C,
0x01,0x38,0x00,0x01,
0x18,0x03,0x00,0x00,
0x01,0x48,0x01,0x18,
0x00,0x0d,
};
#endif

#ifdef AT_VGA
unsigned char TCON_data[]={  //20~35
0x21,0x7d,0x60,0x01,
0x06,0x60,0x01,0x5C,
0x01,0x38,0x00,0x01,
0x18,0x03,0x00,0x00,
0x01,0x48,0x01,0x18,
0x00,0x06};
/* double frequency
unsigned char TCON_data[]={  //20~35
0x21,0x7D,0xc3,0x02,
0x1B,0xc3,0x02,0x5e,
0x02,0x93,0x01,0x04,
0x00,0x03,0x00,0x00,
0x00,0xf9,0x01,0xC9,
0x00,0x01,};*/
#endif

#ifdef KVGA
unsigned char TCON_data[]={  //20~35
0x21,0x7f,0x02,0x02,
0x0C,0x02,0x02,0xf2,
0x01,0x29,0x00,0x04,
0x18,0x03,0x00,0x00,
0x01,0xFB,0x01,0x37,
0x00,0x06,};
#endif

#ifdef L_VGA

unsigned char TCON_data[]={  //20~35
0x21,0x51,0x02,0x02,
0x16/*0x0c*/,0x02,0x02,0xf2,
0x01,0x29,0x00,0x04,
0x18,0x03,0x00,0x00,
0x01,0x37,0x00,0x00,
0x02,0x06,};
/*
unsigned char TCON_data[]={  //20~35
0x21,0x51,0x02,0x02,
0x0C,0x02,0x02,0xff,
0x01,0x14,0x00,0x04,
0x18,0x03,0x00,0x00,
0x01,0x06,0x00,0x5f,
0x02,0x06,};*/
#endif
#endif

void InitTW101(void)
{

#ifdef AU_35
	I2CWriteByte(TW101,0xcb, 0x66);
	I2CWriteByte(TW101,0xcc, 0x42);
	I2CWriteByte(TW101,0x79, 0x0d);
#endif
	I2CWriteByte(TW101,ADC_ROFF, 0x60);
	I2CWriteByte(TW101,ADC_GOFF, 0x60);
	I2CWriteByte(TW101,ADC_BOFF, 0x60);

	I2CWriteByte(TW101,0x97, 0x95);
    I2CWriteByte(TW101,0x98, 0xCC);//930813 Ruby

    I2CWriteByte(TW101+4,0x24, 0xe9);
	I2CWriteByte(TW101+4,0x25, 0x0F);
///////////////////////
	I2CWriteByte(TW101,0xd, 0x20);
////

	I2CWriteByte(TW101,0xe0, 0x92);
	I2CWriteByte(TW101,0xe2, 0x00);//bruce, 2005-07-09
	I2CWriteByte(TW101,0x11, 0x05);//
//Source Select--S Video
	I2CWriteByte(TW101,0x18, 0x00);
	I2CWriteByte(TW101,0x19, 0x07);

    I2CWriteByte(TW101,0x1a, 0x87);

//Video Register Page Setted
	I2CWriteByte(TW101+4,0x02, 0x4b);
	I2CWriteByte(TW101+4,0x2e, 0x82);
    I2CWriteByte(TW101+4,0x2f, 0x30);
	I2CWriteByte(TW101+4,0x3f, 0x00);
	I2CWriteByte(TW101+4,0xc0, 0x14);
//	I2CWriteByte(TW101+4,0xc1, 0x01);
	I2CWriteByte(TW101+4,0xe0, 0x10);

	I2CWriteByte(TW101+4,0x00, 0x01);

	I2CWriteByte(TW101+4,0x03, 0x03);

//	I2CWriteByte(TW101+4,0x01, 0x01);
	I2CWriteByte(TW101+4,0x0c, 0x8a);
	I2CWriteByte(TW101+4,0x18, 0x21);
	I2CWriteByte(TW101+4,0x19, 0xf0);
	I2CWriteByte(TW101+4,0x1a, 0x7c);
	I2CWriteByte(TW101+4,0x1b, 0x0f);

	I2CWriteByte(TW101+4,0x30,0x24);// 0x22);
	I2CWriteByte(TW101+4,0x31, 0x61);
	I2CWriteByte(TW101+4,0x82, 0x42);
//Enable CSC
	I2CWriteByte(TW101,0x90, 0x06);
	I2CWriteByte(TW101,0x91, 0x00);
//DSP Clock
	I2CWriteByte(TW101, PLLDIV_F,DFDIV_40);
	I2CWriteByte(TW101, PLLDIV_I,DIDIV);

    I2CWriteByte(TW101, PLLDIV_O,DODIV);
	I2CWriteByte(TW101,0xc2, 0x00);

//DSP Colck Polarity
	I2CWriteByte(TW101,0xc1, 0xc8);
//Display contrast setting
	I2CWriteByte(TW101,0x0a,0x71);

//H&V Main Display Pixel Clock Setted

	I2CWriteByte(TW101,0xdc, (uCHAR)(H_Size&0xFF));//H Size
	I2CWriteByte(TW101,0xdd, (uCHAR)(H_Size>>8));

	I2CWriteByte(TW101,0xde, (uCHAR)(V_Size&0xFF));//V Size
	I2CWriteByte(TW101,0xdf, (uCHAR)(V_Size>>8));


//H&V Display Pixel Clock Setted
#ifdef AU_35

    for(i=0;i<16;i++)
        I2CWriteByte(TW101, Timing_index+i, Output_timing[i]);

    I2CWriteByte(TW101,0x84,0x00);
    I2CWriteByte(TW101,0x85,0x30);
#else
	I2CWriteByte(TW101,0xb0, 0x20);//H Start
	I2CWriteByte(TW101,0xb1, 0x00);
	I2CWriteByte(TW101,0xb2, 0x20);//V Start
	I2CWriteByte(TW101,0xb3, 0x00);
	I2CWriteByte(TW101,0xb4, (uCHAR)(H_Size&0xFF));//H Width
	I2CWriteByte(TW101,0xb5, (uCHAR)(H_Size>>8));
    I2CWriteByte(TW101,0xb6, (uCHAR)(V_Size&0xFF));
    I2CWriteByte(TW101,0xb7, (uCHAR)(V_Size>>8));
	I2CWriteByte(TW101,0xb8, 0x10);//H Total
	I2CWriteByte(TW101,0xb9, 0x05);
	I2CWriteByte(TW101,0xba, 0x2f);//V Total
	I2CWriteByte(TW101,0xbb, 0x02);
	I2CWriteByte(TW101,0xbc, 0x20);//HSYNC Width
	I2CWriteByte(TW101,0xbd, 0x00);
	I2CWriteByte(TW101,0xbe, 0x04);//VSYNC Width
	I2CWriteByte(TW101,0xbf, 0x00);

#endif
//Scaling
	I2CWriteByte(TW101,0x72, 0x33);//H Scale
	I2CWriteByte(TW101,0x73, 0x73);
	I2CWriteByte(TW101,0x74, 0x00);//V Scale
	I2CWriteByte(TW101,0x75, 0x40);


//LineBuffer Prefill
	I2CWriteByte(TW101,0x84, 0x00);
	I2CWriteByte(TW101,0x85, 0x01);

	I2CWriteByte(TW101,0xe1, 0xa0);
	I2CWriteByte(TW101,0x50, 0x10);
	I2CWriteByte(TW101,0x38, 0x50);
	I2CWriteByte(TW101,0x39, 0x00);
	I2CWriteByte(TW101,0x3a, 0x20);
	I2CWriteByte(TW101,0x3b, 0x03);
#ifdef TCON 
	    I2CWriteByte(TW101,0xe0, 0x9f);
	    I2CWriteByte(TW101,0xe1, 0xf4);
#else
	I2CWriteByte(TW101,0xe0, 0x9c);
	I2CWriteByte(TW101,0xe1, 0x00);
#endif
#ifdef ROTATE
#ifdef KVGA
   SET_Dismod();
#endif
#endif
   
#ifdef OUT_PIN_CONF
	    I2CWriteByte(TW101,0xe1, OUT_PIN_CONF);
#endif    
    I2CWriteByte(TW101, 0x9c, 0x02);

    I2CWriteByte(TW101, 0x90, 0x06);
    I2CWriteByte(TW101+4, 0x04, 0xDD);   
  	I2CWriteByte(TW101+4, 0x10, 0x27);
	I2CWriteByte(TW101+4, 0x00, 0x00);
	I2CWriteByte(TW101+4, 0x03, 0x00);
	I2CWriteByte(TW101+4, 0x02, 0x4B);

	I2CWriteByte(TW101+4, 0x11, 0xb9);

//    I2CWriteByte(TW101+4, 0x07, 0x01);
    


//    I2CWriteByte(TW101, 0x65, 0x88);    //Ruby 2004-08-30
//   I2CWriteByte(TW101, 0x66, 0xff);    //Keep in default 2004-10-06 //Ruby 2004-08-30

    I2CWriteByte(TW101,0x30,(I2CReadByte(TW101, 0x30)|0x01));    //De-Interlace enable
	I2CWriteByte(TW101+4,0x01,(I2CReadByte(TW101+4, 0x01)|0x01));//Color


/////////////for image quality
//    I2CWriteByte(TW101+4,0x80,0x05);  //04); 2004-10-16//  0x05);     //For char clear    2004-10-07
  	I2CWriteByte(TW101+4,0x80,0x07);
    I2CWriteByte(TW101,0x6C,0x80);// 2004-10-16 0x40);
    I2CWriteByte(TW101+4,0x07,0x02/*|0x20*/);   // for color bar clear    2004-10-07
/*

    I2CWriteByte(TW101, 0x60, 0x01);
    I2CWriteByte(TW101,0x61,0x8F);    //For char clear    2004-10-08
    I2CWriteByte(TW101,0x62,0x0F);     //For char clear    2004-10-08
    I2CWriteByte(TW101,0x63,0x0F);     //For char clear    2004-10-08
    I2CWriteByte(TW101,0x64,0x04);     //For char clear    2004-10-08
	I2CWriteByte(TW101,0x66,0x88);     //For color clear    2004-11-25 enable DCTI
*/

    I2CWriteByte(TW101, 0x60, 0x00);
    I2CWriteByte(TW101,0x65,0x08);    //For char clear    2004-10-08
    I2CWriteByte(TW101,0x66,0x88);     //For char clear    2004-10-08

	I2CWriteByte(TW101,0x1C,0xF0);// 2004-10-16 0xF0);     //For image quality    2004-10-08
	I2CWriteByte(TW101+4,0x08,0x50);//0x80);//2004-10-16 0x6A);     //For image quality    2004-10-09
	I2CWriteByte(TW101+4,0x0a,0x60);//0x80);//2004-10-16 0x6A); 
	I2CWriteByte(TW101+4,0x09,0x10);//0x20);//2004-10-16 0x18);     //add by zjl For image quality    2004-10-09
/*	I2CWriteByte(TW101+4,0x08,0x70);//0x80);//2004-10-16 0x6A);     //For image quality    2004-10-09
	I2CWriteByte(TW101+4,0x0a,0x66);//0x80);//2004-10-16 0x6A); 
	I2CWriteByte(TW101+4,0x09,0x00);
	I2CWriteByte(TW101+4,0x0b,0x07);//0x80);//2004-10-16 0x6A);    
	I2CWriteByte(TW101+4,0x0c,0x72);//0x80);//2004-10-16 0x6A); 	//add by zjl
*/
	#ifdef AT_56
		I2CWriteByte(TW101+4,0x09,0x18);
		I2CWriteByte(TW101,0xc7,0x10);
		I2CWriteByte(TW101,0xc8,0x57);
		I2CWriteByte(TW101,0xc9,0x02);
		I2CWriteByte(TW101,0xca,0x0f);
		I2CWriteByte(TW101,0xcb,0x16);
		I2CWriteByte(TW101,0xcc,0x32);
		I2CWriteByte(TW101,0xe0,0x9f);
	#endif
    #ifdef AU_35
		I2CWriteByte(TW101+4,0x08,0x40);
		I2CWriteByte(TW101+4,0x09,0x18);
    #endif
//	page2 0x24 need to fine tune in assamble time, because different decoder will nedd different value
//  working with 0x24 	I2CWriteByte(TW101, 0x66, 0xff);    //Keep in default 2004-10-06 //Ruby 2004-08-30

	I2CWriteByte(TW101, 0x9d, 0x10);//0x10);
	I2CWriteByte(TW101, 0x9e, 0x80);//0x80);
	I2CWriteByte(TW101, 0x9f, 0x80);//0x80);
#ifdef LG_7
    I2CWriteByte(TW101+4, 0x07, 0x21);
    I2CWriteByte(TW101, 0xb2, 0x11);
    I2CWriteByte(TW101, 0xb8, 0x6a);
	I2CWriteByte(TW101+4, 0x80, 0x25);
#endif
	I2CWriteByte(TW101+1,0xD3, 0x1f);
}

#ifdef TCON     // for TCON only
void TconInit(void)
{
    for(i=0;i<22;i++)
        I2CWriteByte(TW101+2, TCON_index+i, TCON_data[i]);
#ifdef TIME_PROTOCOL
    I2CWriteByte(TW101+2, 0x21, TIME_PROTOCOL);
#endif
#ifdef GATE_PREDRIVE
    I2CWriteByte(TW101+2, 0x2D, GATE_PREDRIVE);
#endif
#ifdef AU_35
//    I2CWriteByte(TW101+2, 0x20, 0x21);
//    I2CWriteByte(TW101+2, 0x21, 0x7d);
    I2CWriteByte(TW101, 0xe0, 0xbf);
    I2CWriteByte(TW101, 0xe1, 0xf4);
	#ifdef PVI_35_480   // for PVI 3.5' 480*234 ,change by cwyong 2005-9-1
		I2CWriteByte(TW101,0xc7,0x10);
		I2CWriteByte(TW101,0xe0,0x9f);
	#endif
#endif
#ifdef PVI_5