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📄 system.h

📁 宏芯T102芯片驱动(51单片机作主控)
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//---------------------------------------------------------------------------
// Terawins Inc. Company Confidential Strictly Private
//
// $Archive: System.h $
// $Revision: 1.0 $
// $Author: JoannW $
// $Date: 2002/06/18 $
//
// --------------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------------------------
// Copyright 2002(c) Terawins Inc.
// This is an unpublished work.
// --------------------------------------------------------------------------

#if !defined(__SYSTEM_H__)
#define __SYSTEM_H__
//***************************************************************
//Test
//***************************************************************
#define AUTO_DETECT
#define Guanlin

//#define TV
#ifdef TV
	#define PAL
//	#define NTSC
#define PAL_I  0x0e
#define PAL_DK 0x0f
#endif
#define T515
#define T102

/////////////////PANEL config

//#define LOAD_TIME
#define NEW_BOARD

#define AU_7  
//#define PANASONIC_7  
//#define PVI_7
//#define LG_7  
//#define AT_56
/*--------------------------------------------------*/
// define PVI_5 and PVI_35_480 for PVI 3.5' 960*234 //
//#define AU_35
//#define PVI_35_480 
/*-------------------------------------------------*/
//#define TOSHIBA_7
//#define LG_656 
/*--------------------------------------------------*/
// define PVI_5 and PVI_35_960 for PVI 3.5' 960*234 //
//#define PVI_5
//#define	PVI_35_960
/*-------------------------------------------------*/


#ifdef PVI_5
#define Panel_ID 0x1a
#define AT_VGA
#define TCON
#define TIME_PROTOCOL 0x75
#define GATE_PREDRIVE 0x03
#define HALF_SAMPLE   0x20
#define OUT_PIN_CONF  0xf0
#endif

#ifdef AT_56
#define Panel_ID 0x05
#define AT_VGA
#define TCON
#define TIME_PROTOCOL 0x7D
#define GATE_PREDRIVE 0x03
#endif

#ifdef AU_35
#define Panel_ID 0x06
#define A35_VGA
#define TCON
#define TIME_PROTOCOL 0x7D
#define OUT_PIN_CONF  0xF0
#define GATE_PREDRIVE 0x03
#endif

#ifdef PVI_35
#define Panel_ID 0x0a
#define P35_VGA
#define TCON
#define TIME_PROTOCOL 0x78 //0x7D
#define OUT_PIN_CONF  0xAC //0xF0
#define GATE_PREDRIVE 0x03
#endif

#ifdef AU_7
#define Panel_ID 0x01
#define KVGA
#define TCON
#define ROTATE
#define TIME_PROTOCOL 0x7D
#define GATE_PREDRIVE 0x03
#endif

#ifdef PANASONIC_7
#define Panel_ID 0x02
#define KVGA
#define TCON
#define TIME_PROTOCOL 0x7F
#define OUT_PIN_CONF  0xE4
#define GATE_PREDRIVE 0x05
#endif


#ifdef  TOSHIBA_7
#define Panel_ID 0x08
#define KVGA
#define TCON
#define TIME_PROTOCOL 0x7f
#define OUT_PIN_CONF  0xE4
#define GATE_PREDRIVE 0x03
#endif

#ifdef PVI_7
#define Panel_ID 0x03
#define KVGA
#define TCON
#define TIME_PROTOCOL 0x7F
#define OUT_PIN_CONF  0xE4
#define GATE_PREDRIVE 0x03
#endif

#ifdef LG_7
#define Panel_ID 0x04
#define KVGA
#define TCON
#define TIME_PROTOCOL 0x3f  //0x33 //0x7F
#define OUT_PIN_CONF  0xEC
#define GATE_PREDRIVE 0x03
#endif


#ifdef LG_656
#define Panel_ID 0x04
#define L_VGA
#define TCON
#define TIME_PROTOCOL 0x51  //0x33 //0x7F
#define OUT_PIN_CONF  0xE8
#define GATE_PREDRIVE 0x03
#endif


/////////////////////////////////
//#define component


//***************************************************************
//Test
//***************************************************************
#define DELAY_LINES  4
//***************************************************************
//Source
//***************************************************************
#ifdef NEW_BOARD
typedef enum{
#ifdef T102
#ifdef TV
    isrcTV=0x01,
	isrcCVIDEO2,
#else
	isrcCVIDEO1=0x01,
	isrcCVIDEO2,
#endif 
	isrc_end ,
//	isrcCVIDEO3,
	isrcSVIDEO,
	
	isrcSVIDE1,
#endif
#ifdef T515
#ifdef T102	
    isrc_T515_CVIDEO1,
#else
    //isrc_T515_CVIDEO1=0x01,
#endif
	isrc_T515_CVIDEO2,
#endif
    
	
	isrc_T515_SVIDEO

}VIDEOINPUT;
#else
typedef enum{
#ifdef TV
    isrcTV=0x01,
	isrcCVIDEO2,
#else
	isrcCVIDEO1=0x01,
	isrcCVIDEO2,
#endif 

	isrcCVIDEO3,
	isrcCVIDEO4,
	isrcSVIDEO,

#ifdef T515	
    isrc_T515_CVIDEO1,
    
#endif

    isrc_end ,
	isrc_T515_CVIDEO2,
	isrc_T515_SVIDEO

}VIDEOINPUT;
#endif

typedef enum{
S_NTSC=0x01,
S_PAL,
S_SECAM,
S_END
}VIDEOSTANDARD;

typedef enum{
L_ENGLISH=0x01,
L_CHINESE,
L_END
}VIDEOLANGUGE;

typedef enum{
M_STANDARD=0x01,
M_SOFT,
M_VIVID,
M_BRIGHT,
M_PP,
M_END
}VIDEOMODE;
//***************************************************************
//define Port
//***************************************************************

sbit 	BKLIGHT_EN		= P1^0;

sbit	AUDIO_MUTE		= P1^3;
sbit	CHIP_RESET      = P1^4;
sbit 	VIDEO_RESET		= P1^5;//P0^2; //P1^3;

sbit    Audio0		      = P0^5;
sbit    Audio1			= P0^6;

sbit 	LED_GREEN		= P2^6;
sbit 	LED_RED		    = P2^7;

sbit	Tpoint			= P1^2;

sbit	kBLACK = P2 ^ 5;
sbit	LEFT_RIGHT 		= P0^0;
sbit	UP_DOWN			= P0^1;
/************************************
         System
************************************/
#define TIMER0
#define INTERRUPT1
#define TIMER1

#define XCLK			27000000 

#ifdef KVGA
#define DFDIV_40		21//27	 	//40MHz 0xC8

#define DIDIV			2//3    	//0xC9
#define DODIV			3//3    	//0xCA
#endif

#ifdef WVGA
#define DFDIV_40		43	 	//40MHz

#define DIDIV			2    	//0xC9
#define DODIV			2    	//0xCA
#endif

#ifdef WXGA
#ifdef AU_12
#define DFDIV_40		42	 	//40MHz
#else
#define DFDIV_40		46	 	//40MHz
#endif
#define DIDIV			2    	//0xC9
#define DODIV			1    	//0xCA
#endif

#ifdef WXGA1
#define DFDIV_40		42	 	//40MHz
#define DIDIV			2    	//0xC9
#define DODIV			1    	//0xCA
#endif


#ifdef AT_VGA
    #define DFDIV_40		0x1c//27	 	//40MHz 0xC8
    #define DIDIV			2//3    	//0xC9
    #define DODIV			7 //3//3    	//0xCA
#endif

#ifdef A35_VGA
    #define DFDIV_40		0x2b//0x1C	 	//40MHz 0xC8
    #define DIDIV			2   	//0xC9
    #define DODIV			0x03//0x0b    	//0xCA
#endif

#ifdef P35_VGA
    #define DFDIV_40		0x1C	 	//40MHz 0xC8
    #define DIDIV			2   	//0xC9
    #define DODIV			0x07    	//0xCA
#endif

#ifdef L_VGA
#define DFDIV_40		0x13//27	 	//40MHz 0xC8

#define DIDIV			2//3    	//0xC9
#define DODIV			3//3    	//0xCA
#endif

#ifdef AT_VGA
#define DRDIV			(1<<(DODIV&0x03+1))
#define DNDIV_40		((float)(DFDIV_40+2)/(DIDIV+2)/DRDIV)/2
#else
#define DRDIV			(1<<(DODIV+1))
#define DNDIV_40		((float)(DFDIV_40+2)/(DIDIV+2)/DRDIV)
#endif
#define BACKLIGHT
#define POWER_ON_SEQUENCE

#define NVRAM

/************************************
         Display
************************************/

#ifdef AUDIO_AVAILABLE
	#define VPWME	0x10
	#define PVOL_BGHS_SEL	0x04
#else
	#define VPWME	0x00
	#define PVOL_BGHS_SEL 	0x00
#endif                                                                                                                                                                                                                                                                                                                                                                                                                                                                                           

#ifdef TMDS
	#define TMDS_LOW		39000000
	#define TMDS_HIGH       80000000
#endif

//#define	TCONPOWER			1 //this if for chip bug May.08
#ifdef TCON
  	#define	TCONPOWER		1
	#define TCON_GO_SYNC 	1
#else
  	#define	TCONPOWER		0
	#define TCON_GO_SYNC 	0
#endif


#define DIGITAL_BRIGHT
#define DIGITAL_CONTRAST

#define GAMMA_EN
#ifdef GAMMA_EN
//	#define GAMMAR_ONLY
//	#define GAMMAG_ONLY
//	#define GAMMAB_ONLY
	#define GAMMARGB_TOGETHER
#endif

#define FAILSAFE_EN
#ifdef FAILSAFE_EN
	#define VSYNC_MAX		85
#endif

//#define INTERLACED
/************************************
         Input Source
************************************/
#define VIDEO_AVAILABLE				1
#define TV_AVAILABLE				1
/************************************
         Software Config
************************************/
#define FAILSAFE_ADJ_EN
	#define FAILSAFE_ADJ_POS 		0x01
	#define FAILSAFE_ADJ_FREQ		0x02
	#define FAILSAFE_ADJ_PHASE		0x04
#define SUBSAMPLE_ADJ_EN
	#define SUBSAMPLE_ADJ_POS		0x01
	#define SUBSAMPLE_ADJ_FREQ		0x02
	#define SUBSAMPLE_ADJ_PHASE		0x04
#define DUBLESAMPLE_ADJ_EN
	#define DUBLESAMPLE_ADJ_POS		0x01
	#define DUBLESAMPLE_ADJ_FREQ	0x02
	#define DUBLESAMPLE_ADJ_PHASE	0x04
//#define DOSMODE_ADJ_EN
	#define DOSMODE_ADJ_POS			0x01
	#define DOSMODE_ADJ_FREQ      	0x02
	#define DOSMODE_ADJ_PHASE      	0x04

#define	GM_RGB_ALL_SAME
#define ADJ_DIGITAL				1
#define ADJ_ADC					0

//Ruby add 2005-06-07
typedef enum{
 ScaleFULL = 0x00,
 Scale4_3        ,   
/*#ifdef T515   
 Scale1_1        ,
#endif  */    
 ScaleEnd        ,  
 Scale16_9		 
}Scale_Type;


#ifdef AT_VGA
    #define H_Size    320 //640 //0xdc 0xdd  //0xb4 0xb5  //0xdc 0xdd
    #define V_Size    234 //0xde 0xdf  //0xb6 0xb7  //0xde 0xdf
    #define H_Size43  430//382//0x0138 312
#endif


#ifdef A35_VGA
    #define H_Size    160 
    #define V_Size    234 
    #define H_Size43  160
#endif

#ifdef P35_VGA
    #define H_Size    320 
    #define V_Size    234 
    #define H_Size43  320
#endif

#ifdef L_VGA
    #define H_Size    400 
    #define V_Size    234 
    #define H_Size43  320
#endif

#ifdef KVGA
#define H_Size    480 //0xdc 0xdd  //0xb4 0xb5  //0xdc 0xdd
#define V_Size    234 //0xde 0xdf  //0xb6 0xb7  //0xde 0xdf
#define H_Size43  360
#endif

#ifdef WVGA
#define H_Size    800 
#define V_Size    480 
#define H_Size43  702
#endif

#ifdef WXGA
#define H_Size    0x0500 //0xdc 0xdd  //0xb4 0xb5  //0xdc 0xdd
    #ifdef AU_12
		#define V_Size  0x0320 //0xde 0xdf  //0xb6 0xb7  //0xde 0xdf 
    #else
		#define V_Size  0x02ff //0xde 0xdf  //0xb6 0xb7  //0xde 0xdf
    #endif
#define H_Size43  0x0500
#endif

#ifdef WXGA1
#define H_Size    1024
#define V_Size    768 //0xde 0xdf  //0xb6 0xb7  //0xde 0xdf
#define H_Size43  800
#endif

#endif // __SYSTEM_H__

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