prev_cmp_led.qmsg

本源码已通过调试,里面有简单的分频做法和点亮18个LED灯

{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F672C6 " "Info: Device EP2C50F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C70F672C6 " "Info: Device EP2C70F672C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0 "" 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0}
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Info: Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ E3 " "Info: Pin ~ASDO~ is reserved at location E3" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ D3 " "Info: Pin ~nCSO~ is reserved at location D3" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS150p/nCEO~ AE24 " "Info: Pin ~LVDS150p/nCEO~ is reserved at location AE24" {  } {  } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0}  } {  } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0}
{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "1 20 " "Warning: No exact pin location assignment(s) for 1 pins of 20 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk_50mhz " "Info: Pin clk_50mhz not assigned to an exact location on the device" {  } { { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 2 -1 0 } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50mhz } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50mhz } "NODE_NAME" } }  } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0}  } {  } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_50mhz (placed in PIN N25 (CLK4, LVDSCLK2p, Input)) " "Info: Automatically promoted node clk_50mhz (placed in PIN N25 (CLK4, LVDSCLK2p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G6 " "Info: Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G6" {  } {  } 0 0 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "" 0}  } { { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 2 -1 0 } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50mhz } "NODE_NAME" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50mhz } "NODE_NAME" } }  } 0 0 "Automatically promoted node %1!s! %2!s!" 0 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" {  } {  } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" {  } {  } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 0 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "" 0}
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Extra Info: Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 0 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "" 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "00:00:00 " "Info: Finished register packing: elapsed time is 00:00:00" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0}  } {  } 0 0 "Finished register packing: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.955 ns register register " "Info: Estimated most critical path is register to register delay of 1.955 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_led:shift_led\|led_out\[1\] 1 REG LAB_X41_Y1 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X41_Y1; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[1\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift_led:shift_led|led_out[1] } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.393 ns) + CELL(0.376 ns) 0.769 ns shift_led:shift_led\|Equal0~169 2 COMB LAB_X40_Y1 1 " "Info: 2: + IC(0.393 ns) + CELL(0.376 ns) = 0.769 ns; Loc. = LAB_X40_Y1; Fanout = 1; COMB Node = 'shift_led:shift_led\|Equal0~169'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.769 ns" { shift_led:shift_led|led_out[1] shift_led:shift_led|Equal0~169 } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.410 ns) 1.306 ns shift_led:shift_led\|Equal0~173 3 COMB LAB_X40_Y1 1 " "Info: 3: + IC(0.127 ns) + CELL(0.410 ns) = 1.306 ns; Loc. = LAB_X40_Y1; Fanout = 1; COMB Node = 'shift_led:shift_led\|Equal0~173'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.537 ns" { shift_led:shift_led|Equal0~169 shift_led:shift_led|Equal0~173 } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.438 ns) 1.871 ns shift_led:shift_led\|Equal0~174 4 COMB LAB_X40_Y1 1 " "Info: 4: + IC(0.127 ns) + CELL(0.438 ns) = 1.871 ns; Loc. = LAB_X40_Y1; Fanout = 1; COMB Node = 'shift_led:shift_led\|Equal0~174'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { shift_led:shift_led|Equal0~173 shift_led:shift_led|Equal0~174 } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.955 ns shift_led:shift_led\|led_out\[0\] 5 REG LAB_X40_Y1 3 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 1.955 ns; Loc. = LAB_X40_Y1; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { shift_led:shift_led|Equal0~174 shift_led:shift_led|led_out[0] } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.308 ns ( 66.91 % ) " "Info: Total cell delay = 1.308 ns ( 66.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.647 ns ( 33.09 % ) " "Info: Total interconnect delay = 0.647 ns ( 33.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.955 ns" { shift_led:shift_led|led_out[1] shift_led:shift_led|Equal0~169 shift_led:shift_led|Equal0~173 shift_led:shift_led|Equal0~174 shift_led:shift_led|led_out[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 0 " "Info: Average interconnect usage is 0% of the available device resources. Peak interconnect usage is 0%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X33_Y0 X43_Y11 " "Info: The peak interconnect region extends from location X33_Y0 to location X43_Y11" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}