prev_cmp_led.tan.qmsg

本源码已通过调试,里面有简单的分频做法和点亮18个LED灯

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_50mhz register register shift_led:shift_led\|led_out\[6\] shift_led:shift_led\|led_out\[0\] 420.17 MHz Internal " "Info: Clock \"clk_50mhz\" Internal fmax is restricted to 420.17 MHz between source register \"shift_led:shift_led\|led_out\[6\]\" and destination register \"shift_led:shift_led\|led_out\[0\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.918 ns + Longest register register " "Info: + Longest register to register delay is 1.918 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_led:shift_led\|led_out\[6\] 1 REG LCFF_X36_Y35_N21 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y35_N21; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[6\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift_led:shift_led|led_out[6] } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.344 ns) + CELL(0.398 ns) 0.742 ns shift_led:shift_led\|Equal0~170 2 COMB LCCOMB_X36_Y35_N24 1 " "Info: 2: + IC(0.344 ns) + CELL(0.398 ns) = 0.742 ns; Loc. = LCCOMB_X36_Y35_N24; Fanout = 1; COMB Node = 'shift_led:shift_led\|Equal0~170'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.742 ns" { shift_led:shift_led|led_out[6] shift_led:shift_led|Equal0~170 } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.275 ns) + CELL(0.410 ns) 1.427 ns shift_led:shift_led\|Equal0~173 3 COMB LCCOMB_X36_Y35_N26 1 " "Info: 3: + IC(0.275 ns) + CELL(0.410 ns) = 1.427 ns; Loc. = LCCOMB_X36_Y35_N26; Fanout = 1; COMB Node = 'shift_led:shift_led\|Equal0~173'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.685 ns" { shift_led:shift_led|Equal0~170 shift_led:shift_led|Equal0~173 } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.257 ns) + CELL(0.150 ns) 1.834 ns shift_led:shift_led\|Equal0~174 4 COMB LCCOMB_X36_Y35_N6 1 " "Info: 4: + IC(0.257 ns) + CELL(0.150 ns) = 1.834 ns; Loc. = LCCOMB_X36_Y35_N6; Fanout = 1; COMB Node = 'shift_led:shift_led\|Equal0~174'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.407 ns" { shift_led:shift_led|Equal0~173 shift_led:shift_led|Equal0~174 } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.918 ns shift_led:shift_led\|led_out\[0\] 5 REG LCFF_X36_Y35_N7 3 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 1.918 ns; Loc. = LCFF_X36_Y35_N7; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { shift_led:shift_led|Equal0~174 shift_led:shift_led|led_out[0] } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.042 ns ( 54.33 % ) " "Info: Total cell delay = 1.042 ns ( 54.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.876 ns ( 45.67 % ) " "Info: Total interconnect delay = 0.876 ns ( 45.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.918 ns" { shift_led:shift_led|led_out[6] shift_led:shift_led|Equal0~170 shift_led:shift_led|Equal0~173 shift_led:shift_led|Equal0~174 shift_led:shift_led|led_out[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.918 ns" { shift_led:shift_led|led_out[6] shift_led:shift_led|Equal0~170 shift_led:shift_led|Equal0~173 shift_led:shift_led|Equal0~174 shift_led:shift_led|led_out[0] } { 0.000ns 0.344ns 0.275ns 0.257ns 0.000ns } { 0.000ns 0.398ns 0.410ns 0.150ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50mhz destination 2.672 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_50mhz\" to destination register is 2.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_50mhz 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_50mhz'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50mhz } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_50mhz~clkctrl 2 COMB CLKCTRL_G3 18 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_50mhz clk_50mhz~clkctrl } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.537 ns) 2.672 ns shift_led:shift_led\|led_out\[0\] 3 REG LCFF_X36_Y35_N7 3 " "Info: 3: + IC(1.018 ns) + CELL(0.537 ns) = 2.672 ns; Loc. = LCFF_X36_Y35_N7; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[0\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.555 ns" { clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.49 % ) " "Info: Total cell delay = 1.536 ns ( 57.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.136 ns ( 42.51 % ) " "Info: Total interconnect delay = 1.136 ns ( 42.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.672 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.672 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50mhz source 2.672 ns - Longest register " "Info: - Longest clock path from clock \"clk_50mhz\" to source register is 2.672 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_50mhz 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_50mhz'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50mhz } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_50mhz~clkctrl 2 COMB CLKCTRL_G3 18 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_50mhz clk_50mhz~clkctrl } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.018 ns) + CELL(0.537 ns) 2.672 ns shift_led:shift_led\|led_out\[6\] 3 REG LCFF_X36_Y35_N21 3 " "Info: 3: + IC(1.018 ns) + CELL(0.537 ns) = 2.672 ns; Loc. = LCFF_X36_Y35_N21; Fanout = 3; REG Node = 'shift_led:shift_led\|led_out\[6\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.555 ns" { clk_50mhz~clkctrl shift_led:shift_led|led_out[6] } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.49 % ) " "Info: Total cell delay = 1.536 ns ( 57.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.136 ns ( 42.51 % ) " "Info: Total interconnect delay = 1.136 ns ( 42.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.672 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[6] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.672 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[6] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.672 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.672 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.672 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[6] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.672 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[6] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.918 ns" { shift_led:shift_led|led_out[6] shift_led:shift_led|Equal0~170 shift_led:shift_led|Equal0~173 shift_led:shift_led|Equal0~174 shift_led:shift_led|led_out[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.918 ns" { shift_led:shift_led|led_out[6] shift_led:shift_led|Equal0~170 shift_led:shift_led|Equal0~173 shift_led:shift_led|Equal0~174 shift_led:shift_led|led_out[0] } { 0.000ns 0.344ns 0.275ns 0.257ns 0.000ns } { 0.000ns 0.398ns 0.410ns 0.150ns 0.084ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.672 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.672 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[0] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.672 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[6] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.672 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[6] } { 0.000ns 0.000ns 0.118ns 1.018ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift_led:shift_led|led_out[0] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { shift_led:shift_led|led_out[0] } {  } {  } "" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_50mhz led_out\[17\] shift_led:shift_led\|led_out\[17\] 9.158 ns register " "Info: tco from clock \"clk_50mhz\" to destination pin \"led_out\[17\]\" through register \"shift_led:shift_led\|led_out\[17\]\" is 9.158 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_50mhz source 2.671 ns + Longest register " "Info: + Longest clock path from clock \"clk_50mhz\" to source register is 2.671 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk_50mhz 1 CLK PIN_P2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P2; Fanout = 1; CLK Node = 'clk_50mhz'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_50mhz } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk_50mhz~clkctrl 2 COMB CLKCTRL_G3 18 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G3; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { clk_50mhz clk_50mhz~clkctrl } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.537 ns) 2.671 ns shift_led:shift_led\|led_out\[17\] 3 REG LCFF_X35_Y35_N31 2 " "Info: 3: + IC(1.017 ns) + CELL(0.537 ns) = 2.671 ns; Loc. = LCFF_X35_Y35_N31; Fanout = 2; REG Node = 'shift_led:shift_led\|led_out\[17\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { clk_50mhz~clkctrl shift_led:shift_led|led_out[17] } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.51 % ) " "Info: Total cell delay = 1.536 ns ( 57.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.135 ns ( 42.49 % ) " "Info: Total interconnect delay = 1.135 ns ( 42.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.671 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[17] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.671 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[17] } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.237 ns + Longest register pin " "Info: + Longest register to pin delay is 6.237 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns shift_led:shift_led\|led_out\[17\] 1 REG LCFF_X35_Y35_N31 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y35_N31; Fanout = 2; REG Node = 'shift_led:shift_led\|led_out\[17\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { shift_led:shift_led|led_out[17] } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 54 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.459 ns) + CELL(2.778 ns) 6.237 ns led_out\[17\] 2 PIN PIN_AA13 0 " "Info: 2: + IC(3.459 ns) + CELL(2.778 ns) = 6.237 ns; Loc. = PIN_AA13; Fanout = 0; PIN Node = 'led_out\[17\]'" {  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.237 ns" { shift_led:shift_led|led_out[17] led_out[17] } "NODE_NAME" } } { "../led.v" "" { Text "E:/altera/71/quartus/led.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.778 ns ( 44.54 % ) " "Info: Total cell delay = 2.778 ns ( 44.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.459 ns ( 55.46 % ) " "Info: Total interconnect delay = 3.459 ns ( 55.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.237 ns" { shift_led:shift_led|led_out[17] led_out[17] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.237 ns" { shift_led:shift_led|led_out[17] led_out[17] } { 0.000ns 3.459ns } { 0.000ns 2.778ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.671 ns" { clk_50mhz clk_50mhz~clkctrl shift_led:shift_led|led_out[17] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.671 ns" { clk_50mhz clk_50mhz~combout clk_50mhz~clkctrl shift_led:shift_led|led_out[17] } { 0.000ns 0.000ns 0.118ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.537ns } "" } } { "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.237 ns" { shift_led:shift_led|led_out[17] led_out[17] } "NODE_NAME" } } { "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.237 ns" { shift_led:shift_led|led_out[17] led_out[17] } { 0.000ns 3.459ns } { 0.000ns 2.778ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 28 15:51:57 2007 " "Info: Processing ended: Thu Jun 28 15:51:57 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}