📄 led.v.bak
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module led(reset,clk_50mhz,led_out);
input reset,clk_50mhz;
output[17:0] led_out;
wire clk_5hz;
shift_led shift_led(clk_50mhz,reset,led_out);
divider_5hz divider_5hz(clk_50mhz,clk_5hz);
endmodule
//divider 50MHz-->5Hz
module divider_5hz(clk_50mhz,clk_5hz);
input clk_50mhz;
output clk_5hz;
reg clk_5hz;
reg [25:0] q;
always@(posedge clk_50mhz)
begin
if(q[23]&q[20]&q[19]&q[15]&q[12]&q[10]&q[9]&q[7])
q=0;
else
q=q+1;
end
always@(q)
begin
if(q[23]&q[20]&q[19]&q[15]&q[12]&q[10]&q[9]&q[7])
clk_5hz=1'b1;
else
clk_5hz=1'b0;
end
endmodule
//shift left
module shift_led(clk_5hz,reset,led_out);
input clk_5hz,reset;
output led_out;
reg[17:0] led_out;
always@(posedge clk_5hz or negedge reset)
begin
if(~reset)
led_out=000000000000000001;
else
begin
if(led_out==5'h20000)
led_out=5'h00001;
else
led_out=led_out<<1;
end
end
endmodule
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