led.tan.rpt

本源码已通过调试,里面有简单的分频做法和点亮18个LED灯

; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[17] ; shift_led:shift_led|led_out[0]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.995 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[10] ; shift_led:shift_led|led_out[11] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.868 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[3]  ; shift_led:shift_led|led_out[4]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.867 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[7]  ; shift_led:shift_led|led_out[8]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.860 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[1]  ; shift_led:shift_led|led_out[2]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.843 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[16] ; shift_led:shift_led|led_out[0]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.833 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[2]  ; shift_led:shift_led|led_out[3]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.824 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[15] ; shift_led:shift_led|led_out[16] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.736 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[11] ; shift_led:shift_led|led_out[12] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.733 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[0]  ; shift_led:shift_led|led_out[1]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.726 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[6]  ; shift_led:shift_led|led_out[7]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.700 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[9]  ; shift_led:shift_led|led_out[10] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.698 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[14] ; shift_led:shift_led|led_out[15] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.697 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[13] ; shift_led:shift_led|led_out[14] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.693 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[12] ; shift_led:shift_led|led_out[13] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.560 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[4]  ; shift_led:shift_led|led_out[5]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.556 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[5]  ; shift_led:shift_led|led_out[6]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.555 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[8]  ; shift_led:shift_led|led_out[9]  ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.552 ns                ;
; N/A   ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; shift_led:shift_led|led_out[16] ; shift_led:shift_led|led_out[17] ; clk_50mhz  ; clk_50mhz ; None                        ; None                      ; 0.544 ns                ;
+-------+------------------------------------------------+---------------------------------+---------------------------------+------------+-----------+-----------------------------+---------------------------+-------------------------+


+------------------------------------------------------------------------------------------------+
; tco                                                                                            ;
+-------+--------------+------------+---------------------------------+-------------+------------+
; Slack ; Required tco ; Actual tco ; From                            ; To          ; From Clock ;
+-------+--------------+------------+---------------------------------+-------------+------------+
; N/A   ; None         ; 8.637 ns   ; shift_led:shift_led|led_out[6]  ; led_out[6]  ; clk_50mhz  ;
; N/A   ; None         ; 7.986 ns   ; shift_led:shift_led|led_out[3]  ; led_out[3]  ; clk_50mhz  ;
; N/A   ; None         ; 7.776 ns   ; shift_led:shift_led|led_out[1]  ; led_out[1]  ; clk_50mhz  ;
; N/A   ; None         ; 7.774 ns   ; shift_led:shift_led|led_out[0]  ; led_out[0]  ; clk_50mhz  ;
; N/A   ; None         ; 7.748 ns   ; shift_led:shift_led|led_out[4]  ; led_out[4]  ; clk_50mhz  ;
; N/A   ; None         ; 7.733 ns   ; shift_led:shift_led|led_out[7]  ; led_out[7]  ; clk_50mhz  ;
; N/A   ; None         ; 7.686 ns   ; shift_led:shift_led|led_out[5]  ; led_out[5]  ; clk_50mhz  ;
; N/A   ; None         ; 7.672 ns   ; shift_led:shift_led|led_out[2]  ; led_out[2]  ; clk_50mhz  ;
; N/A   ; None         ; 7.310 ns   ; shift_led:shift_led|led_out[16] ; led_out[16] ; clk_50mhz  ;
; N/A   ; None         ; 7.070 ns   ; shift_led:shift_led|led_out[17] ; led_out[17] ; clk_50mhz  ;
; N/A   ; None         ; 7.020 ns   ; shift_led:shift_led|led_out[15] ; led_out[15] ; clk_50mhz  ;
; N/A   ; None         ; 6.951 ns   ; shift_led:shift_led|led_out[14] ; led_out[14] ; clk_50mhz  ;
; N/A   ; None         ; 6.597 ns   ; shift_led:shift_led|led_out[13] ; led_out[13] ; clk_50mhz  ;
; N/A   ; None         ; 6.596 ns   ; shift_led:shift_led|led_out[12] ; led_out[12] ; clk_50mhz  ;
; N/A   ; None         ; 6.585 ns   ; shift_led:shift_led|led_out[10] ; led_out[10] ; clk_50mhz  ;
; N/A   ; None         ; 6.581 ns   ; shift_led:shift_led|led_out[9]  ; led_out[9]  ; clk_50mhz  ;
; N/A   ; None         ; 6.580 ns   ; shift_led:shift_led|led_out[11] ; led_out[11] ; clk_50mhz  ;
; N/A   ; None         ; 6.574 ns   ; shift_led:shift_led|led_out[8]  ; led_out[8]  ; clk_50mhz  ;
+-------+--------------+------------+---------------------------------+-------------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu Jun 28 16:42:35 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off led -c led --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk_50mhz" is an undefined clock
Info: Clock "clk_50mhz" Internal fmax is restricted to 420.17 MHz between source register "shift_led:shift_led|led_out[5]" and destination register "shift_led:shift_led|led_out[0]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.041 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y1_N27; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[5]'
            Info: 2: + IC(0.518 ns) + CELL(0.398 ns) = 0.916 ns; Loc. = LCCOMB_X40_Y1_N0; Fanout = 1; COMB Node = 'shift_led:shift_led|Equal0~170'
            Info: 3: + IC(0.245 ns) + CELL(0.393 ns) = 1.554 ns; Loc. = LCCOMB_X40_Y1_N12; Fanout = 1; COMB Node = 'shift_led:shift_led|Equal0~173'
            Info: 4: + IC(0.253 ns) + CELL(0.150 ns) = 1.957 ns; Loc. = LCCOMB_X40_Y1_N16; Fanout = 1; COMB Node = 'shift_led:shift_led|Equal0~174'
            Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.041 ns; Loc. = LCFF_X40_Y1_N17; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[0]'
            Info: Total cell delay = 1.025 ns ( 50.22 % )
            Info: Total interconnect delay = 1.016 ns ( 49.78 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk_50mhz" to destination register is 2.694 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50mhz'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'
                Info: 3: + IC(1.040 ns) + CELL(0.537 ns) = 2.694 ns; Loc. = LCFF_X40_Y1_N17; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[0]'
                Info: Total cell delay = 1.536 ns ( 57.02 % )
                Info: Total interconnect delay = 1.158 ns ( 42.98 % )
            Info: - Longest clock path from clock "clk_50mhz" to source register is 2.694 ns
                Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50mhz'
                Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'
                Info: 3: + IC(1.040 ns) + CELL(0.537 ns) = 2.694 ns; Loc. = LCFF_X40_Y1_N27; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[5]'
                Info: Total cell delay = 1.536 ns ( 57.02 % )
                Info: Total interconnect delay = 1.158 ns ( 42.98 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clk_50mhz" to destination pin "led_out[6]" through register "shift_led:shift_led|led_out[6]" is 8.637 ns
    Info: + Longest clock path from clock "clk_50mhz" to source register is 2.694 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk_50mhz'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 18; COMB Node = 'clk_50mhz~clkctrl'
        Info: 3: + IC(1.040 ns) + CELL(0.537 ns) = 2.694 ns; Loc. = LCFF_X40_Y1_N15; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[6]'
        Info: Total cell delay = 1.536 ns ( 57.02 % )
        Info: Total interconnect delay = 1.158 ns ( 42.98 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.693 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X40_Y1_N15; Fanout = 3; REG Node = 'shift_led:shift_led|led_out[6]'
        Info: 2: + IC(2.895 ns) + CELL(2.798 ns) = 5.693 ns; Loc. = PIN_AD21; Fanout = 0; PIN Node = 'led_out[6]'
        Info: Total cell delay = 2.798 ns ( 49.15 % )
        Info: Total interconnect delay = 2.895 ns ( 50.85 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
    Info: Allocated 112 megabytes of memory during processing
    Info: Processing ended: Thu Jun 28 16:42:37 2007
    Info: Elapsed time: 00:00:02