led.map.rpt

本源码已通过调试,里面有简单的分频做法和点亮18个LED灯

; HDL message level                                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Use smart compilation                                                          ; Off                ; Off                ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                     ;
+----------------------------------+-----------------+------------------------+------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+------------------------------+
; ../led.v                         ; yes             ; User Verilog HDL File  ; E:/altera/71/quartus/led.v   ;
+----------------------------------+-----------------+------------------------+------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Estimated Total logic elements              ; 18        ;
;                                             ;           ;
; Total combinational functions               ; 7         ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 5         ;
;     -- 3 input functions                    ; 1         ;
;     -- <=2 input functions                  ; 1         ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 7         ;
;     -- arithmetic mode                      ; 0         ;
;                                             ;           ;
; Total registers                             ; 18        ;
;     -- Dedicated logic registers            ; 18        ;
;     -- I/O registers                        ; 0         ;
;                                             ;           ;
; I/O pins                                    ; 20        ;
; Maximum fan-out node                        ; clk_50mhz ;
; Maximum fan-out                             ; 18        ;
; Total fan-out                               ; 96        ;
; Average fan-out                             ; 2.13      ;
+---------------------------------------------+-----------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                              ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name      ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+--------------+
; |led                       ; 7 (0)             ; 18 (0)       ; 0           ; 0            ; 0       ; 0         ; 20   ; 0            ; |led                     ; work         ;
;    |shift_led:shift_led|   ; 7 (7)             ; 18 (18)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |led|shift_led:shift_led ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 18    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 18    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; shift_led:shift_led|led_out[0]         ; 3       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Thu Jun 28 16:40:29 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off led -c led
Warning (10227): Verilog HDL Port Declaration warning at led.v(40): data type declaration for "led_out" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at led.v(42): "led_out" is declared here
Warning (10229): Verilog HDL Expression warning at led.v(50): truncated literal to match 5 bits
Info: Found 3 design units, including 3 entities, in source file ../led.v
    Info: Found entity 1: led
    Info: Found entity 2: divider_5hz
    Info: Found entity 3: shift_led
Info: Elaborating entity "led" for the top level hierarchy
Info: Elaborating entity "shift_led" for hierarchy "shift_led:shift_led"
Info: Elaborating entity "divider_5hz" for hierarchy "divider_5hz:divider_5hz"
Warning (10230): Verilog HDL assignment warning at led.v(25): truncated value with size 32 to match size of target (26)
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 43 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 18 output pins
    Info: Implemented 23 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 131 megabytes of memory during processing
    Info: Processing ended: Thu Jun 28 16:40:34 2007
    Info: Elapsed time: 00:00:05