dff8.rpt

8位移位寄存器

        | | | | | | | | | +------------- LC19 ~179~1
        | | | | | | | | | | +----------- LC17 ~188~1
        | | | | | | | | | | | +--------- LC22 ~197~1
        | | | | | | | | | | | | +------- LC23 ~206~1
        | | | | | | | | | | | | | +----- LC25 ~215~1
        | | | | | | | | | | | | | | +--- LC29 ~224~1
        | | | | | | | | | | | | | | | +- LC20 ~233~1
        | | | | | | | | | | | | | | | | 
        | | | | | | | | | | | | | | | |   Other LABs fed by signals
        | | | | | | | | | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | | | | | | | | | A B |     Logic cells that feed LAB 'B':

Pin
4    -> * * * * * * * * * * * * * * * * | * * | <-- clear
LC16 -> - - - - - - - * * - - - - - - - | - * | <-- ~164~1
LC4  -> - - - - - - * - - * - - - - - - | - * | <-- ~176~1
LC2  -> - - - - - * - - - - * - - - - - | - * | <-- ~185~1
LC1  -> - - - - * - - - - - - * - - - - | - * | <-- ~194~1
LC5  -> - - - * - - - - - - - - * - - - | - * | <-- ~203~1
LC6  -> - - * - - - - - - - - - - * - - | - * | <-- ~212~1
LC8  -> - * - - - - - - - - - - - - * - | - * | <-- ~221~1
LC12 -> * - - - - - - - - - - - - - - * | - * | <-- ~230~1


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                                  d:\vhdl\dff8.rpt
dff8

** EQUATIONS **

clear    : INPUT;
clk      : INPUT;
Din0     : INPUT;
Din1     : INPUT;
Din2     : INPUT;
Din3     : INPUT;
Din4     : INPUT;
Din5     : INPUT;
Din6     : INPUT;
Din7     : INPUT;

-- Node name is 'Dout0' 
-- Equation name is 'Dout0', location is LC030, type is output.
 Dout0   = LCELL( _EQ001 $  GND);
  _EQ001 = !clear &  _LC012;

-- Node name is 'Dout1' 
-- Equation name is 'Dout1', location is LC026, type is output.
 Dout1   = LCELL( _EQ002 $  GND);
  _EQ002 = !clear &  _LC008;

-- Node name is 'Dout2' 
-- Equation name is 'Dout2', location is LC032, type is output.
 Dout2   = LCELL( _EQ003 $  GND);
  _EQ003 = !clear &  _LC006;

-- Node name is 'Dout3' 
-- Equation name is 'Dout3', location is LC018, type is output.
 Dout3   = LCELL( _EQ004 $  GND);
  _EQ004 = !clear &  _LC005;

-- Node name is 'Dout4' 
-- Equation name is 'Dout4', location is LC024, type is output.
 Dout4   = LCELL( _EQ005 $  GND);
  _EQ005 = !clear &  _LC001;

-- Node name is 'Dout5' 
-- Equation name is 'Dout5', location is LC027, type is output.
 Dout5   = LCELL( _EQ006 $  GND);
  _EQ006 = !clear &  _LC002;

-- Node name is 'Dout6' 
-- Equation name is 'Dout6', location is LC028, type is output.
 Dout6   = LCELL( _EQ007 $  GND);
  _EQ007 = !clear &  _LC004;

-- Node name is 'Dout7' 
-- Equation name is 'Dout7', location is LC031, type is output.
 Dout7   = LCELL( _EQ008 $  GND);
  _EQ008 = !clear &  _LC016;

-- Node name is '~164~1' 
-- Equation name is '~164~1', location is LC016, type is buried.
-- synthesized logic cell 
_LC016   = LCELL( _EQ009 $  _LC021);
  _EQ009 = !clear &  clk &  Din7 & !_LC021
         # !clear &  clk & !Din7 &  _LC021;

-- Node name is '~170~1' 
-- Equation name is '~170~1', location is LC021, type is buried.
-- synthesized logic cell 
_LC021   = LCELL( _EQ010 $  GND);
  _EQ010 = !clear &  _LC016;

-- Node name is '~176~1' 
-- Equation name is '~176~1', location is LC004, type is buried.
-- synthesized logic cell 
_LC004   = LCELL( _EQ011 $  _LC019);
  _EQ011 = !clear &  clk &  Din6 & !_LC019
         # !clear &  clk & !Din6 &  _LC019;

-- Node name is '~179~1' 
-- Equation name is '~179~1', location is LC019, type is buried.
-- synthesized logic cell 
_LC019   = LCELL( _EQ012 $  GND);
  _EQ012 = !clear &  _LC004;

-- Node name is '~185~1' 
-- Equation name is '~185~1', location is LC002, type is buried.
-- synthesized logic cell 
_LC002   = LCELL( _EQ013 $  _LC017);
  _EQ013 = !clear &  clk &  Din5 & !_LC017
         # !clear &  clk & !Din5 &  _LC017;

-- Node name is '~188~1' 
-- Equation name is '~188~1', location is LC017, type is buried.
-- synthesized logic cell 
_LC017   = LCELL( _EQ014 $  GND);
  _EQ014 = !clear &  _LC002;

-- Node name is '~194~1' 
-- Equation name is '~194~1', location is LC001, type is buried.
-- synthesized logic cell 
_LC001   = LCELL( _EQ015 $  _LC022);
  _EQ015 = !clear &  clk &  Din4 & !_LC022
         # !clear &  clk & !Din4 &  _LC022;

-- Node name is '~197~1' 
-- Equation name is '~197~1', location is LC022, type is buried.
-- synthesized logic cell 
_LC022   = LCELL( _EQ016 $  GND);
  _EQ016 = !clear &  _LC001;

-- Node name is '~203~1' 
-- Equation name is '~203~1', location is LC005, type is buried.
-- synthesized logic cell 
_LC005   = LCELL( _EQ017 $  _LC023);
  _EQ017 = !clear &  clk &  Din3 & !_LC023
         # !clear &  clk & !Din3 &  _LC023;

-- Node name is '~206~1' 
-- Equation name is '~206~1', location is LC023, type is buried.
-- synthesized logic cell 
_LC023   = LCELL( _EQ018 $  GND);
  _EQ018 = !clear &  _LC005;

-- Node name is '~212~1' 
-- Equation name is '~212~1', location is LC006, type is buried.
-- synthesized logic cell 
_LC006   = LCELL( _EQ019 $  _LC025);
  _EQ019 = !clear &  clk &  Din2 & !_LC025
         # !clear &  clk & !Din2 &  _LC025;

-- Node name is '~215~1' 
-- Equation name is '~215~1', location is LC025, type is buried.
-- synthesized logic cell 
_LC025   = LCELL( _EQ020 $  GND);
  _EQ020 = !clear &  _LC006;

-- Node name is '~221~1' 
-- Equation name is '~221~1', location is LC008, type is buried.
-- synthesized logic cell 
_LC008   = LCELL( _EQ021 $  _LC029);
  _EQ021 = !clear &  clk &  Din1 & !_LC029
         # !clear &  clk & !Din1 &  _LC029;

-- Node name is '~224~1' 
-- Equation name is '~224~1', location is LC029, type is buried.
-- synthesized logic cell 
_LC029   = LCELL( _EQ022 $  GND);
  _EQ022 = !clear &  _LC008;

-- Node name is '~230~1' 
-- Equation name is '~230~1', location is LC012, type is buried.
-- synthesized logic cell 
_LC012   = LCELL( _EQ023 $  _LC020);
  _EQ023 = !clear &  clk &  Din0 & !_LC020
         # !clear &  clk & !Din0 &  _LC020;

-- Node name is '~233~1' 
-- Equation name is '~233~1', location is LC020, type is buried.
-- synthesized logic cell 
_LC020   = LCELL( _EQ024 $  GND);
  _EQ024 = !clear &  _LC012;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                           d:\vhdl\dff8.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:00


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,647K