📄 dff8.rpt
字号:
Project Information d:\vhdl\dff8.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 05/16/2008 11:03:19
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
DFF8
** DEVICE SUMMARY **
Chip/ Input Output Bidir Shareable
POF Device Pins Pins Pins LCs Expanders % Utilized
dff8 EPM7032LC44-6 10 8 0 24 0 75 %
User Pins: 10 8 0
Device-Specific Information: d:\vhdl\dff8.rpt
dff8
***** Logic for device 'dff8' compiled without errors.
Device: EPM7032LC44-6
Device Options:
Turbo Bit = ON
Security Bit = OFF
R
E
S
c E D
D D l R o
i i e V G G G G G V u
n n a C N N N N N E t
6 7 r C D D D D D D 3
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
Din5 | 7 39 | RESERVED
Din4 | 8 38 | RESERVED
Din3 | 9 37 | RESERVED
GND | 10 36 | RESERVED
Din2 | 11 35 | VCC
Din1 | 12 EPM7032LC44-6 34 | RESERVED
Din0 | 13 33 | Dout4
clk | 14 32 | RESERVED
VCC | 15 31 | Dout1
RESERVED | 16 30 | GND
RESERVED | 17 29 | Dout5
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
R R R R G V D D D R D
E E E E N C o o o E o
S S S S D C u u u S u
E E E E t t t E t
R R R R 2 7 0 R 6
V V V V V
E E E E E
D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: d:\vhdl\dff8.rpt
dff8
** RESOURCE USAGE **
Shareable External
Logic Array Block Logic Cells I/O Pins Expanders Interconnect
A: LC1 - LC16 8/16( 50%) 10/16( 62%) 0/16( 0%) 18/36( 50%)
B: LC17 - LC32 16/16(100%) 8/16( 50%) 0/16( 0%) 9/36( 25%)
Total dedicated input pins used: 0/4 ( 0%)
Total I/O pins used: 18/32 ( 56%)
Total logic cells used: 24/32 ( 75%)
Total shareable expanders used: 0/32 ( 0%)
Total Turbo logic cells used: 24/32 ( 75%)
Total shareable expanders not available (n/a): 0/32 ( 0%)
Average fan-in: 2.66
Total fan-in: 64
Total input pins required: 10
Total output pins required: 8
Total bidirectional pins required: 0
Total logic cells required: 24
Total flipflops required: 0
Total product terms required: 40
Total logic cells lending parallel expanders: 0
Total shareable expanders in database: 0
Synthesized logic cells: 16/ 32 ( 50%)
Device-Specific Information: d:\vhdl\dff8.rpt
dff8
** INPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
4 (1) (A) INPUT 0 0 0 0 0 8 16 clear
14 (10) (A) INPUT 0 0 0 0 0 0 8 clk
13 (9) (A) INPUT 0 0 0 0 0 0 1 Din0
12 (8) (A) INPUT 0 0 0 0 0 0 1 Din1
11 (7) (A) INPUT 0 0 0 0 0 0 1 Din2
9 (6) (A) INPUT 0 0 0 0 0 0 1 Din3
8 (5) (A) INPUT 0 0 0 0 0 0 1 Din4
7 (4) (A) INPUT 0 0 0 0 0 0 1 Din5
6 (3) (A) INPUT 0 0 0 0 0 0 1 Din6
5 (2) (A) INPUT 0 0 0 0 0 0 1 Din7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\dff8.rpt
dff8
** OUTPUTS **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
26 30 B OUTPUT t 0 0 0 1 1 0 0 Dout0
31 26 B OUTPUT t 0 0 0 1 1 0 0 Dout1
24 32 B OUTPUT t 0 0 0 1 1 0 0 Dout2
40 18 B OUTPUT t 0 0 0 1 1 0 0 Dout3
33 24 B OUTPUT t 0 0 0 1 1 0 0 Dout4
29 27 B OUTPUT t 0 0 0 1 1 0 0 Dout5
28 28 B OUTPUT t 0 0 0 1 1 0 0 Dout6
25 31 B OUTPUT t 0 0 0 1 1 0 0 Dout7
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\dff8.rpt
dff8
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(21) 16 A SOFT s t 0 0 0 3 1 1 1 ~164~1
(37) 21 B LCELL s t 0 0 0 1 1 0 1 ~170~1
(7) 4 A SOFT s t 0 0 0 3 1 1 1 ~176~1
(39) 19 B LCELL s t 0 0 0 1 1 0 1 ~179~1
(5) 2 A SOFT s t 0 0 0 3 1 1 1 ~185~1
(41) 17 B LCELL s t 0 0 0 1 1 0 1 ~188~1
(4) 1 A SOFT s t 0 0 0 3 1 1 1 ~194~1
(36) 22 B LCELL s t 0 0 0 1 1 0 1 ~197~1
(8) 5 A SOFT s t 0 0 0 3 1 1 1 ~203~1
(34) 23 B LCELL s t 0 0 0 1 1 0 1 ~206~1
(9) 6 A SOFT s t 0 0 0 3 1 1 1 ~212~1
(32) 25 B LCELL s t 0 0 0 1 1 0 1 ~215~1
(12) 8 A SOFT s t 0 0 0 3 1 1 1 ~221~1
(27) 29 B LCELL s t 0 0 0 1 1 0 1 ~224~1
(17) 12 A SOFT s t 0 0 0 3 1 1 1 ~230~1
(38) 20 B LCELL s t 0 0 0 1 1 0 1 ~233~1
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\vhdl\dff8.rpt
dff8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+--------------- LC16 ~164~1
| +------------- LC4 ~176~1
| | +----------- LC2 ~185~1
| | | +--------- LC1 ~194~1
| | | | +------- LC5 ~203~1
| | | | | +----- LC6 ~212~1
| | | | | | +--- LC8 ~221~1
| | | | | | | +- LC12 ~230~1
| | | | | | | |
| | | | | | | | Other LABs fed by signals
| | | | | | | | that feed LAB 'A'
LC | | | | | | | | | A B | Logic cells that feed LAB 'A':
Pin
4 -> * * * * * * * * | * * | <-- clear
14 -> * * * * * * * * | * - | <-- clk
13 -> - - - - - - - * | * - | <-- Din0
12 -> - - - - - - * - | * - | <-- Din1
11 -> - - - - - * - - | * - | <-- Din2
9 -> - - - - * - - - | * - | <-- Din3
8 -> - - - * - - - - | * - | <-- Din4
7 -> - - * - - - - - | * - | <-- Din5
6 -> - * - - - - - - | * - | <-- Din6
5 -> * - - - - - - - | * - | <-- Din7
LC21 -> * - - - - - - - | * - | <-- ~170~1
LC19 -> - * - - - - - - | * - | <-- ~179~1
LC17 -> - - * - - - - - | * - | <-- ~188~1
LC22 -> - - - * - - - - | * - | <-- ~197~1
LC23 -> - - - - * - - - | * - | <-- ~206~1
LC25 -> - - - - - * - - | * - | <-- ~215~1
LC29 -> - - - - - - * - | * - | <-- ~224~1
LC20 -> - - - - - - - * | * - | <-- ~233~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\vhdl\dff8.rpt
dff8
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC30 Dout0
| +----------------------------- LC26 Dout1
| | +--------------------------- LC32 Dout2
| | | +------------------------- LC18 Dout3
| | | | +----------------------- LC24 Dout4
| | | | | +--------------------- LC27 Dout5
| | | | | | +------------------- LC28 Dout6
| | | | | | | +----------------- LC31 Dout7
| | | | | | | | +--------------- LC21 ~170~1
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -