📄 periph.lst
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C51 COMPILER V8.02 PERIPH 04/02/2008 15:31:31 PAGE 1
C51 COMPILER V8.02, COMPILATION OF MODULE PERIPH
OBJECT MODULE PLACED IN periph.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE periph.c BROWSE DEBUG OBJECTEXTEND
line level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: periph.c
4 // Contents: Hooks required to implement USB peripheral function.
5 //
6 // Copyright (c) 1997 AnchorChips, Inc. All rights reserved
7 //-----------------------------------------------------------------------------
8 #include "fx2.h"
9 #include "fx2regs.h"
10 #include "fx2sdly.h"
11 #include "gpif.h"
12
13 extern BOOL GotSUD; // Received setup data flag
14 extern BOOL Sleep;
15 extern BOOL Rwuen;
16 extern BOOL Selfpwr;
17
18 BYTE Configuration; // Current configuration
19 BYTE AlternateSetting; // Alternate settings
20 BYTE High_Full_Flag;
21
22 extern const char xdata FlowStates[36];
23 //-----------------------------------------------------------------------------
24 // Task Dispatcher hooks
25 // The following hooks are called by the task dispatcher.
26 //-----------------------------------------------------------------------------
27
28 void TD_Init(void) // Called once at startup
29 {
30 1 // set the CPU clock to 48MHz
31 1 CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
32 1 SYNCDELAY;
33 1
34 1
35 1 Rwuen = TRUE; // Enable remote-wakeup
36 1
37 1 // EP2 512 BULK OUT 4x
38 1 SYNCDELAY; // see TRM section 15.14
39 1 EP2CFG = 0xA0; //512PACKET; // BUF[1:0]=00 for 4x buffering
40 1
41 1 // EP4 and EP6 and EP8 are not used in this implementation...
42 1
43 1 SYNCDELAY; //
44 1 EP6CFG = 0xE0; // clear valid bit
45 1
46 1
47 1 SYNCDELAY; //
48 1 FIFORESET = 0x80; // activate NAK-ALL to avoid race conditions
49 1 SYNCDELAY; //
50 1 FIFORESET = 0x02; // reset, FIFO 2
51 1
52 1 SYNCDELAY; //
53 1 FIFORESET = 0x06; // reset, FIFO 6
54 1
55 1 SYNCDELAY; //
C51 COMPILER V8.02 PERIPH 04/02/2008 15:31:31 PAGE 2
56 1 FIFORESET = 0x00; // deactivate NAK-ALL
57 1 SYNCDELAY;
58 1
59 1 // 8-bit bus (WORDWIDE=1)...
60 1 EP2FIFOCFG = 0x10;//AUTO OUT 8-BIT BUS
61 1 SYNCDELAY;
62 1 EP6FIFOCFG = 0x08;//AUTO IN 8-BIT BUS
63 1 SYNCDELAY;
64 1
65 1 GpifInit();
66 1
67 1 // setup INT4 as internal source for GPIF interrupts
68 1 // using INT4CLR (SFR), automatically enabled
69 1 SYNCDELAY;
70 1 INTSETUP |= 0x03; // Enable INT4 FIFO/GPIF Autovectoring
71 1 SYNCDELAY; // used here as "delay"
72 1 EXIF &= ~0x40; // just in case one was pending...
73 1 SYNCDELAY; // used here as "delay"
74 1 GPIFIRQ = 0x03;
75 1 SYNCDELAY; //
76 1 GPIFIE = 0x03; // Enable GPIFDONE interrupt
77 1 SYNCDELAY; //
78 1 EIE |= 0x04; // Enable INT4 ISR, EIE.2(EIEX4=1)
79 1 }
80
81 void TD_Poll(void) // Called repeatedly while the device is idle
82 {
83 1
84 1 // OEA=0xff;
85 1 // IOA=~(IOA&0x01);
86 1
87 1 if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
88 1 {
89 2 if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
90 2 {
91 3 Peripheral_SetEP2GPIFTC(512); //write 512 byte data to gipf
92 3 Peripheral_FIFOWrite(0);
93 3 }
94 2
95 2 else if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
96 2 {
97 3 Peripheral_SetEP6GPIFTC(512); //read 512 byte data from gipf
98 3 Peripheral_FIFORead(2);
99 3 }
100 2 }
101 1 }
102
103 BOOL TD_Suspend(void) // Called before the device goes into suspend mode
104 {
105 1 return(TRUE);
106 1 }
107
108 BOOL TD_Resume(void) // Called after the device resumes
109 {
110 1 return(TRUE);
111 1 }
112 #define TESTING_GPIF // NOTE: Comment this line out for frameworks based firmware
113 // See the example GPIF Tool Utility under Application
114 // Reference Material for more advanced development info
115 #ifdef TESTING_GPIF
116 // TODO: You may add additional code below.
117
C51 COMPILER V8.02 PERIPH 04/02/2008 15:31:31 PAGE 3
118 void OtherInit( void )
119 { // interface initialization
120 1 // ...see TD_Init( );
121 1 }
122
123 // Set EP2GPIF Transaction Count
124 void Peripheral_SetEP2GPIFTC( WORD xfrcnt )
125 {
126 1 SYNCDELAY; //
127 1 EP2GPIFTCH = xfrcnt >> 8; // setup transaction count
128 1 SYNCDELAY; //
129 1 EP2GPIFTCL = ( BYTE )xfrcnt;
130 1 }
131
132 // Set EP6GPIF Transaction Count
133 void Peripheral_SetEP6GPIFTC( WORD xfrcnt )
134 {
135 1 SYNCDELAY; //
136 1 EP6GPIFTCH = xfrcnt >> 8; // setup transaction count
137 1 SYNCDELAY; //
138 1 EP6GPIFTCL = ( BYTE )xfrcnt;
139 1 }
140
141 #define GPIF_FLGSELPF 0
142 #define GPIF_FLGSELEF 1
143 #define GPIF_FLGSELFF 2
144
145 // Set EP2GPIF Decision Point FIFO Flag Select (PF, EF, FF)
146 void SetEP2GPIFFLGSEL( WORD DP_FIFOFlag )
147 {
148 1 EP2GPIFFLGSEL = DP_FIFOFlag;
149 1 }
150
151 // Set EP6GPIF Decision Point FIFO Flag Select (PF, EF, FF)
152 void SetEP6GPIFFLGSEL( WORD DP_FIFOFlag )
153 {
154 1 EP6GPIFFLGSEL = DP_FIFOFlag;
155 1 }
156
157
158 // Set EP2GPIF Programmable Flag STOP, overrides Transaction Count
159 void SetEP2GPIFPFSTOP( void )
160 {
161 1 EP2GPIFPFSTOP = 0x01;
162 1 }
163
164 // Set EP6GPIF Programmable Flag STOP, overrides Transaction Count
165 void SetEP6GPIFPFSTOP( void )
166 {
167 1 EP6GPIFPFSTOP = 0x01;
168 1 }
169
170 #define GPIFTRIGWR 0
171 #define GPIFTRIGRD 4
172
173
174 // write byte(s)/word(s) to PERIPHERAL, using GPIF and EPxFIFO
175 // if EPx WORDWIDE=0 then write byte(s)
176 // if EPx WORDWIDE=1 then write word(s)
177 void Peripheral_FIFOWrite( BYTE FIFO_EpNum )
178 {
179 1 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 Done bit
C51 COMPILER V8.02 PERIPH 04/02/2008 15:31:31 PAGE 4
180 1 {
181 2 ;
182 2 }
183 1
184 1 // trigger FIFO write transaction(s), using SFR
185 1 GPIFTRIG = FIFO_EpNum; // R/W=0, EP[1:0]=FIFO_EpNum for EPx write(s)
186 1 }
187
188 // read byte(s)/word(s) from PERIPHERAL, using GPIF and EPxFIFO
189 // if EPx WORDWIDE=0 then read byte(s)
190 // if EPx WORDWIDE=1 then read word(s)
191 void Peripheral_FIFORead( BYTE FIFO_EpNum )
192 {
193 1 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
194 1 {
195 2 ;
196 2 }
197 1
198 1 // trigger FIFO read transaction(s), using SFR
199 1 GPIFTRIG = GPIFTRIGRD | FIFO_EpNum; // R/W=1, EP[1:0]=FIFO_EpNum for EPx read(s)
200 1 }
201
202
203 #endif
204 //-----------------------------------------------------------------------------
205 // Device Request hooks
206 // The following hooks are called by the end point 0 device request parser.
207 //-----------------------------------------------------------------------------
208
209 BOOL DR_GetDescriptor(void)
210 {
211 1 return(TRUE);
212 1 }
213
214 BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
215 {
216 1 Configuration = SETUPDAT[2];
217 1 if(High_Full_Flag == 1)
218 1 {
219 2 SYNCDELAY; //
220 2 EP2AUTOINLENH = 0x02; //ep2 auto commit length 512
221 2 SYNCDELAY;
222 2 EP2AUTOINLENL = 0x00;
223 2 SYNCDELAY;
224 2 EP6AUTOINLENH = 0x02; //ep6 auto commit length 512
225 2 SYNCDELAY;
226 2 EP6AUTOINLENL = 0x00;
227 2 SYNCDELAY;
228 2 }
229 1 else
230 1 {
231 2 SYNCDELAY; //
232 2 EP2AUTOINLENH = 0x00; //ep2 auto commit length 512
233 2 SYNCDELAY;
234 2 EP2AUTOINLENL = 0x40;
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