ph8550_sc.h

smart card智能卡的读写测试程序

/****************************************************************************
 * 
 * Copyright (c) 2007 - 2009 Aero-Info Corp. All rights reserved. 
 *
 ****************************************************************************/
 
/****************************************************************************
 * 
 * FILENAME
 *     Ph8550_sc.h
 *
 * VERSION
 *     1.1
 * 
 * DESCRIPTION
 *     Smart Card driver supported by Philips Ph8550 Chip.
 *
 * MengFanjie
 *************************************************************************/

#ifndef _Ph8550_sc_H
#define _Ph8550_sc_H

#include <linux/config.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/fcntl.h>
#include <linux/fs.h>  
#include <linux/init.h>
#include <asm/irq.h>
#include <asm/string.h>
#include <linux/devfs_fs_kernel.h>

#define SMARTCARD_IRQ_NO      25             //PNX8550_INT_ISO_UART1 
#define SMARTCARD_MAJOR       96
//#define DEBUG     

/* register map for Ph8550 */
#define UART1_PH_ADDR           (0xbbe00000) /*PNX8550 Ph_Address*/

#define RER                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043000)   /*Reset_Register*/
#define CCR                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043004)   /*Clock Configure Register*/
#define PDR                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043008)   /*Programmable Divider Register*/
#define UCR2                    *(volatile unsigned int *)(UART1_PH_ADDR + 0x04300c)   /*Uart configure Register 2*/
#define DRA                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043010)   /*DMA Read Address Register*/
#define GTR                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043014)   /*Guard Time Register*/
#define UCR1                    *(volatile unsigned int *)(UART1_PH_ADDR + 0x043018)   /*Uart configure Register 1*/
#define DLR                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x04301c)   /*DMA Length Register*/
#define TOC                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043020)   /*Timeout Configure Register*/
#define TOR1                    *(volatile unsigned int *)(UART1_PH_ADDR + 0x043024)   /*Timeout Register 1*/
#define TOR2                    *(volatile unsigned int *)(UART1_PH_ADDR + 0x043028)   /*Timeout Register 2*/
#define TOR3                    *(volatile unsigned int *)(UART1_PH_ADDR + 0x04302c)   /*Timeout Register 3*/
#define MSR                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043030)   /*Mixed Status Register*/
#define FCR                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043030)   /*FIFO Control Register, the address is same as MSR???*/
#define UTR                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043034)   /*Uart Transmit Register*/
#define URR                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043034)   /*Uart Received Register*/
#define USR                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043038)   /*Uart Status Register*/
#define DWA                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x04303c)   /*DMA Write Address Register*/
#define CRE                     *(volatile unsigned int *)(UART1_PH_ADDR + 0x043040)   /*Command Register*/

#define SCIF_INT_STATUS         *(volatile unsigned int *)(UART1_PH_ADDR + 0x043fe0)   /*SCIF_INT_STATUS, ONLY READ*/
#define SCIF_INT_ENABLE         *(volatile unsigned int *)(UART1_PH_ADDR + 0x043fe4)   /*SCIF_INT_ENABLE*/
#define SCIF_INT_CLEAR          *(volatile unsigned int *)(UART1_PH_ADDR + 0x043fe8)   /*SCIF_INT_CLEAR*/
#define SCIF_INT_SET            *(volatile unsigned int *)(UART1_PH_ADDR + 0x043fec)   /*SCIF_INT_SET*/

#define SCIF_POWERDOWN          *(volatile unsigned int *)(UART1_PH_ADDR + 0x043ff4)   /*SCIF_POWERDOWN*/
#define SCIF_MODULE_ID	        *(volatile unsigned int *)(UART1_PH_ADDR + 0x043ffc)   /*SCIF_MODULE_ID, the ID value is 0x01062100*/

#define CLK_UART1_CTL           *(volatile unsigned int *)(UART1_PH_ADDR + 0x04771C)
#define CLK_SMART1_CTL          *(volatile unsigned int *)(UART1_PH_ADDR + 0x047728)
#define MAX_BUF_LEN	255
#define MAX_ATR_LEN    33

#define SC_IOC_WARMACTIVATE            0
#define SC_IOC_DEACTIVATE              1
#define SC_IOC_ATRPROC		       2
#define SC_IOC_GETPPSRESULT            3
#define SC_IOC_GETAPDUSULT             4
#define SC_IOC_SETAPDUCMD              5
#define SC_IOC_SETAPDUCMDNUM           6
#define SC_IOC_SETPARAMETER            7
#define SC_IOC_GETATR                  8
#define SC_IOC_EXECUTECMD              9
#define SC_IOC_GETSTATUS               10
#define SC_IOC_GETCARDEXIST            11


#define SC_ERROR_RW_PE                       2
#define SC_ERROR_RW_OVR                      3
#define SC_ERROR_RW_OUTTIME                  5
#define SC_ERROR_KNTOUSER                    7  
#define SC_ERROR_USERTOKN                    8
#define SC_ERROR_NOCARD                      9  
#define SC_ERROR_PPS_SET_BAUDRATE            10  
#define SC_ERROR_PPS_TREAT_BAUDRATE          11 
#define SC_ERROR_PPS_DEFAULT_BAUDRATE        12 
#define SC_ERROR_PPS_GT_BAUDRATE             13
#define SC_ERROR_PPS_CHECK                   14 
#define SC_ERROR_PPS_PROTOCOL                15 
#define SC_ERROR_CTL_CMDMUN                  16 
#define SC_ERROR_SET_READERPARA              17
#define SC_ERROR_VERIFY_ATRBUF               18
#define SC_ERROR_RW_NOCARD                   19
#define SC_ERROR_ATR_PROTOCOL                20 

struct sc_div_clk_Hz
{
	unsigned char   ac , multiple;
}supported_div_Hz[] = {
	{0, 2},
	{1, 4},
	{2, 6},
	{3, 8},
	{4, 12},
	{5, 16},
	{6, 24},
	{7, 32}
};
 
/* this variable depend on reader chip */
struct sc_baudrate
{		
	int Ps_Pd, fi,di, psc, pdr;
}supported_baudrate[] = {
  
	{372, 0, 1, 31, 12},
	{186, 0, 2, 31, 6},
	{93 , 0, 3, 31, 3},
	{31 , 0, 8, 31, 1},
	
	{372, 1, 1, 31, 12},	
	{186, 1, 2, 31, 6},	
	{93, 1, 3, 31, 3},	
	{31, 1, 8, 31, 1},
	
	{558, 2, 1, 31, 18},	
	{279, 2, 2, 31, 9},

	{744, 3, 1, 31, 24},	
	{372, 3, 2, 31, 12},
	{186, 3, 3, 31, 6},	
	{93,  3, 4, 31, 3},	
	{62,  3, 8, 31, 2},	

	{1116,4, 1, 31, 36},
	{558, 4, 2, 31, 18},	
	{279, 4, 3, 31, 9},	
	{93,  4, 8, 31, 3},	

	{1488,5, 1, 31, 48},
	{744 ,5, 2, 31, 24},	
	{372 ,5, 3, 31, 12},	
	{186 ,5, 4, 31, 6},	
	{93  ,5, 5, 31, 3},
	{124 ,5, 8, 31, 4},	

	{1860,6, 1, 31, 60},	
	{930 ,6, 2, 31, 30},	
	{465 ,6, 3, 31, 15},
	{155 ,6, 8, 31, 5},	
	{93  ,6, 9, 31, 3},	

	{512, 9, 1, 32, 16},	
	{256, 9, 2, 32, 8},
	{128, 9, 3, 32, 4},	
	{64, 9, 4, 32, 2},	
	{32, 9, 5, 32, 1},	

	{768, 10,1, 32, 24},
	{384, 10,2, 32, 12},	
	{192, 10,3, 32, 6},	
	{96 , 10,4, 32, 3},	
	{64 , 10,8, 32, 2},

	{1024,11, 1, 32, 32},	
	{512 ,11, 2, 32, 16},
	{256 ,11, 3, 32, 8},	
	{128 ,11, 4, 32, 4},
	{64  ,11, 5, 32, 2},	
	{32  ,11, 6, 32, 1},	

	{1536, 12,1, 32, 48},	
	{768 , 12,2, 32, 24},
	{384 , 12,3, 32, 12},	
	{192 , 12,4, 32, 6},	
	{96  , 12,5, 32, 3},	
	{128 , 12,8, 32, 4},

	{2048, 13,1, 32, 64},	
	{1024, 13,2, 32, 32},	
	{512 , 13,3, 32, 16},	
	{256 , 13,4, 32, 8},
	{128 , 13,5, 32, 4},	
	{64  , 13,6, 32, 2}
};

typedef struct
{
	unsigned char protocol;
	unsigned char gtr_time;
	unsigned int fi;
	unsigned int di;
	unsigned int div_clock_multiple;
	unsigned char rm_parity;
	unsigned int cwi;
}sc_parameter;

typedef struct
{
	unsigned char atr_buffer[MAX_ATR_LEN];		// atr string 
	unsigned int  atr_len;				// atr len 
	unsigned int openflag;
	unsigned int exist;
	unsigned int fi;
	unsigned int di;
	unsigned char gtr_time;		               // gtr between characters  ( in etus) 
	unsigned char prot;
	unsigned int etu; 		               // card-clk num 
	unsigned int clock;	                       // frequence in KHz 
	unsigned char remove_parity;                   //remove parity bit, if =0, not remove ; if =1 remove
	unsigned int errno;			       // error number 
	unsigned int cwt;		               //timeout value between characters( in etus) 
	volatile unsigned int timeout;	               // 0 - no error 1 - timeout 
}SmartCard_Dev;

#endif