📄 fx2_to_extsyncfifo.c
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#pragma NOIV // Do not generate interrupt vectors
//-----------------------------------------------------------------------------
// File: FX2_to_extsyncFIFO.c
// Contents: Hooks required to implement FX2 GPIF to external sync. FIFO
// interface using CY4265-15AC
//
// Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved
//-----------------------------------------------------------------------------
#include "fx2.h"
#include "fx2regs.h"
#include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech.
// Ref. Manual for usage details.
#define EXTFIFONOTFULL GPIFREADYSTAT & bmBIT1
#define EXTFIFONOTEMPTY GPIFREADYSTAT & bmBIT0
#define GPIFTRIGRD 4
#define GPIF_EP2 0
#define GPIF_EP4 1
#define GPIF_EP6 2
#define GPIF_EP8 3
extern BOOL GotSUD; // Received setup data flag
extern BOOL Sleep;
extern BOOL Rwuen;
extern BOOL Selfpwr;
BYTE Configuration; // Current configuration
BYTE AlternateSetting; // Alternate settings
BOOL in_enable = FALSE; // flag to enable IN transfers
BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
static WORD xdata Tcount = 0; // transaction count
static WORD xFIFOBC_IN = 0x0000; // variable that contains EP6FIFOBCH/L value
//-----------------------------------------------------------------------------
// Task Dispatcher hooks
// The following hooks are called by the task dispatcher.
//-----------------------------------------------------------------------------
//void Setup_FLOWSTATE_Write ( void );
//void Setup_FLOWSTATE_Read ( void );
void GpifInit ();
void TD_Init(void) // Called once at startup
{
// set the CPU clock to 48MHz
CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
SYNCDELAY;
EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
SYNCDELAY;
EP4CFG = 0x00; // EP4 not valid
SYNCDELAY;
EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
SYNCDELAY;
EP8CFG = 0x00; // EP8 not valid
SYNCDELAY;
FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
SYNCDELAY;
FIFORESET = 0x02; // reset EP2 FIFO
SYNCDELAY;
FIFORESET = 0x06; // reset EP6 FIFO
SYNCDELAY;
FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
SYNCDELAY;
EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit
SYNCDELAY;
EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops
SYNCDELAY;
EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
SYNCDELAY;
GpifInit (); // initialize GPIF registers
SYNCDELAY;
EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
SYNCDELAY;
EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
SYNCDELAY;
}
void TD_Poll(void)
{
if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
{
if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
{
if ( EXTFIFONOTFULL ) // if the external FIFO is not full
{
if(enum_high_speed)
{
SYNCDELAY;
GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
}
else
{
SYNCDELAY;
GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
SYNCDELAY;
GPIFTCB0 = 0x20;
SYNCDELAY;
}
// trigger FIFO write transaction(s), using SFR
SYNCDELAY;
GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
SYNCDELAY;
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
;
}
SYNCDELAY;
}
}
}
if(in_enable) // if IN transfers are enabled
{
if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
{
if ( EXTFIFONOTEMPTY ) // if external FIFO is not empty
{
if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
{
if(enum_high_speed)
{
SYNCDELAY;
GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
}
else
{
SYNCDELAY;
GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x0100)
SYNCDELAY;
GPIFTCB0 = 0x00;
SYNCDELAY;
}
GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
SYNCDELAY;
while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
{
;
}
SYNCDELAY;
}
}
}
}
}
BOOL TD_Suspend(void) // Called before the device goes into suspend mode
{
return(TRUE);
}
BOOL TD_Resume(void) // Called after the device resumes
{
return(TRUE);
}
//-----------------------------------------------------------------------------
// Device Request hooks
// The following hooks are called by the end point 0 device request parser.
//-----------------------------------------------------------------------------
BOOL DR_GetDescriptor(void)
{
return(TRUE);
}
BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
{
if( EZUSB_HIGHSPEED( ) )
{ // FX2 enumerated at high speed
SYNCDELAY; //
EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
SYNCDELAY; //
EP6AUTOINLENL = 0x00;
SYNCDELAY;
enum_high_speed = TRUE;
}
else
{ // FX2 enumerated at full speed
SYNCDELAY;
EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
SYNCDELAY;
EP6AUTOINLENL = 0x40;
SYNCDELAY;
enum_high_speed = FALSE;
}
Configuration = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
{
EP0BUF[0] = Configuration;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_SetInterface(void) // Called when a Set Interface command is received
{
AlternateSetting = SETUPDAT[2];
return(TRUE); // Handled by user code
}
BOOL DR_GetInterface(void) // Called when a Set Interface command is received
{
EP0BUF[0] = AlternateSetting;
EP0BCH = 0;
EP0BCL = 1;
return(TRUE); // Handled by user code
}
BOOL DR_GetStatus(void)
{
return(TRUE);
}
BOOL DR_ClearFeature(void)
{
return(TRUE);
}
BOOL DR_SetFeature(void)
{
return(TRUE);
}
#define VX_B2 0xB2 // reset the external FIFO
#define VX_B3 0xB3 // enable IN transfers
#define VX_B4 0xB4 // disable IN transfers
#define VX_B5 0xB5 // read GPIFREADYSTAT register
#define VX_B6 0xB6 // read GPIFTRIG register
//SLAVE FIFO 通道选择命令
//保留跟SLAVE FIFO在VC中使用的读写函数一样而保留的，其实在这只有VX_BB有用
#define VX_BA 0xBA // EP2 OUT
#define VX_BB 0xBB // EP6 IN
BOOL DR_VendorCmnd(void)
{
switch (SETUPDAT[1])
{
case VX_B2:
{
// reset the external FIFO
/*
OEA |= 0x04; // turn on PA2 as output pin
IOA |= 0x04; // pull PA2 high initially
IOA &= 0xFB; // bring PA2 low
EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time
IOA |= 0x04; // bring PA2 high
*/
*EP0BUF = VX_B2;
EP0BCH = 0;
EP0BCL = 1; // Arm endpoint with # bytes to transfer
EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
break;
}
case VX_B3: // enable IN transfers
{
in_enable = TRUE;
*EP0BUF = VX_B3;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
break;
}
case VX_B4: // disable IN transfers
{
in_enable = FALSE;
*EP0BUF = VX_B4;
EP0BCH = 0;
EP0BCL = 1;
EP0CS |= bmHSNAK;
break;
}
case VX_B5: // read GPIFREADYSTAT register
{
EP0BUF[0] = VX_B5;
SYNCDELAY;
EP0BUF[1] = GPIFREADYSTAT;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
break;
}
case VX_B6: // read GPIFTRIG register
{
EP0BUF[0] = VX_B6;
SYNCDELAY;
EP0BUF[1] = GPIFTRIG;
SYNCDELAY;
EP0BCH = 0;
EP0BCL = 2;
EP0CS |= bmHSNAK;
break;
}
//SLAVE FIFO 通道选择命令
//保留跟SLAVE FIFO在VC中使用的读写函数一样而保留的，其实在这只有VX_BB有用
case VX_BA:
{
// reset the external FIFO
// OEA |= 0x03;
// IOA &= ~0x03;
EP0BCL = 1;
break;
}
case VX_BB: // enable IN transfers
{
// OEA |= 0x03;
// IOA &= ~0x03;
// IOA |= 0x02;
in_enable = TRUE;
EP0BCL = 1;
break;
}
default:
return(TRUE);
}
return(FALSE);
}
//-----------------------------------------------------------------------------
// USB Interrupt Handlers
// The following functions are called by the USB interrupt jump table.
//-----------------------------------------------------------------------------
// Setup Data Available Interrupt Handler
void ISR_Sudav(void) interrupt 0
{
GotSUD = TRUE; // Set flag
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUDAV; // Clear SUDAV IRQ
}
// Setup Token Interrupt Handler
void ISR_Sutok(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUTOK; // Clear SUTOK IRQ
}
void ISR_Sof(void) interrupt 0
{
EZUSB_IRQ_CLEAR();
USBIRQ = bmSOF; // Clear SOF IRQ
}
void ISR_Ures(void) interrupt 0
{
// whenever we get a USB reset, we should revert to full speed mode
pConfigDscr = pFullSpeedConfigDscr;
((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
pOtherConfigDscr = pHighSpeedConfigDscr;
((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
EZUSB_IRQ_CLEAR();
USBIRQ = bmURES; // Clear URES IRQ
}
void ISR_Susp(void) interrupt 0
{
Sleep = TRUE;
EZUSB_IRQ_CLEAR();
USBIRQ = bmSUSP;
}
void ISR_Highspeed(void) interrupt 0
{
if (EZUSB_HIGHSPEED())
{
pConfigDscr = pHighSpeedConfigDscr;
((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
pOtherConfigDscr = pFullSpeedConfigDscr;
((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
}
EZUSB_IRQ_CLEAR();
USBIRQ = bmHSGRANT;
}
void ISR_Ep0ack(void) interrupt 0
{
}
void ISR_Stub(void) interrupt 0
{
}
void ISR_Ep0in(void) interrupt 0
{
}
void ISR_Ep0out(void) interrupt 0
{
}
void ISR_Ep1in(void) interrupt 0
{
}
void ISR_Ep1out(void) interrupt 0
{
}
void ISR_Ep2inout(void) interrupt 0
{
}
void ISR_Ep4inout(void) interrupt 0
{
}
void ISR_Ep6inout(void) interrupt 0
{
}
void ISR_Ep8inout(void) interrupt 0
{
}
void ISR_Ibn(void) interrupt 0
{
}
void ISR_Ep0pingnak(void) interrupt 0
{
}
void ISR_Ep1pingnak(void) interrupt 0
{
}
void ISR_Ep2pingnak(void) interrupt 0
{
}
void ISR_Ep4pingnak(void) interrupt 0
{
}
void ISR_Ep6pingnak(void) interrupt 0
{
}
void ISR_Ep8pingnak(void) interrupt 0
{
}
void ISR_Errorlimit(void) interrupt 0
{
}
void ISR_Ep2piderror(void) interrupt 0
{
}
void ISR_Ep4piderror(void) interrupt 0
{
}
void ISR_Ep6piderror(void) interrupt 0
{
}
void ISR_Ep8piderror(void) interrupt 0
{
}
void ISR_Ep2pflag(void) interrupt 0
{
}
void ISR_Ep4pflag(void) interrupt 0
{
}
void ISR_Ep6pflag(void) interrupt 0
{
}
void ISR_Ep8pflag(void) interrupt 0
{
}
void ISR_Ep2eflag(void) interrupt 0
{
}
void ISR_Ep4eflag(void) interrupt 0
{
}
void ISR_Ep6eflag(void) interrupt 0
{
}
void ISR_Ep8eflag(void) interrupt 0
{
}
void ISR_Ep2fflag(void) interrupt 0
{
}
void ISR_Ep4fflag(void) interrupt 0
{
}
void ISR_Ep6fflag(void) interrupt 0
{
}
void ISR_Ep8fflag(void) interrupt 0
{
}
void ISR_GpifComplete(void) interrupt 0
{
}
void ISR_GpifWaveform(void) interrupt 0
{
}
/*
void Setup_FLOWSTATE_Read ( void )
{
FLOWSTATE = FlowStates[18]; // 1000 0011b - FSE=1, FS[2:0]=003
SYNCDELAY;
FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows)
SYNCDELAY;
FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow)
SYNCDELAY;
}
void Setup_FLOWSTATE_Write ( void )
{
FLOWSTATE = FlowStates[27]; // 1000 0001b - FSE=1, FS[2:0]=001
SYNCDELAY;
FLOWEQ0CTL = FlowStates[29]; // CTL0 = 0 when flow condition equals zero (data flows)
SYNCDELAY;
FLOWEQ1CTL = FlowStates[30]; // CTL0 = 1 when flow condition equals one (data does not flow)
SYNCDELAY;
}
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