📄 fx2_to_extsyncfifo.lst
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275 3 IOA &= 0xFB; // bring PA2 low
276 3 EZUSB_Delay (1); // keep PA2 low for ~1ms, more than enough time
277 3 IOA |= 0x04; // bring PA2 high
278 3 */
279 3 *EP0BUF = VX_B2;
280 3 EP0BCH = 0;
281 3 EP0BCL = 1; // Arm endpoint with # bytes to transfer
282 3 EP0CS |= bmHSNAK; // Acknowledge handshake phase of device request
283 3 break;
284 3 }
285 2 case VX_B3: // enable IN transfers
286 2 {
287 3 in_enable = TRUE;
288 3
289 3 *EP0BUF = VX_B3;
290 3 EP0BCH = 0;
291 3 EP0BCL = 1;
292 3 EP0CS |= bmHSNAK;
293 3 break;
294 3 }
295 2 case VX_B4: // disable IN transfers
296 2 {
297 3 in_enable = FALSE;
298 3
299 3 *EP0BUF = VX_B4;
300 3 EP0BCH = 0;
C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 6
301 3 EP0BCL = 1;
302 3 EP0CS |= bmHSNAK;
303 3 break;
304 3 }
305 2 case VX_B5: // read GPIFREADYSTAT register
306 2 {
307 3 EP0BUF[0] = VX_B5;
308 3 SYNCDELAY;
309 3 EP0BUF[1] = GPIFREADYSTAT;
310 3 SYNCDELAY;
311 3 EP0BCH = 0;
312 3 EP0BCL = 2;
313 3 EP0CS |= bmHSNAK;
314 3 break;
315 3 }
316 2 case VX_B6: // read GPIFTRIG register
317 2 {
318 3 EP0BUF[0] = VX_B6;
319 3 SYNCDELAY;
320 3 EP0BUF[1] = GPIFTRIG;
321 3 SYNCDELAY;
322 3 EP0BCH = 0;
323 3 EP0BCL = 2;
324 3 EP0CS |= bmHSNAK;
325 3 break;
326 3 }
327 2
328 2 //SLAVE FIFO 通道选择命令
329 2 //保留跟SLAVE FIFO在VC中使用的读写函数一样而保留的，其实在这只有VX_BB有用
330 2 case VX_BA:
331 2 {
332 3 // reset the external FIFO
333 3 // OEA |= 0x03;
334 3 // IOA &= ~0x03;
335 3 EP0BCL = 1;
336 3 break;
337 3 }
338 2 case VX_BB: // enable IN transfers
339 2 {
340 3 // OEA |= 0x03;
341 3 // IOA &= ~0x03;
342 3 // IOA |= 0x02;
343 3
344 3 in_enable = TRUE;
345 3
346 3 EP0BCL = 1;
347 3 break;
348 3 }
349 2
350 2 default:
351 2 return(TRUE);
352 2 }
353 1
354 1 return(FALSE);
355 1 }
356
357 //-----------------------------------------------------------------------------
358 // USB Interrupt Handlers
359 // The following functions are called by the USB interrupt jump table.
360 //-----------------------------------------------------------------------------
361
362 // Setup Data Available Interrupt Handler
C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 7
363 void ISR_Sudav(void) interrupt 0
364 {
365 1 GotSUD = TRUE; // Set flag
366 1 EZUSB_IRQ_CLEAR();
367 1 USBIRQ = bmSUDAV; // Clear SUDAV IRQ
368 1 }
369
370 // Setup Token Interrupt Handler
371 void ISR_Sutok(void) interrupt 0
372 {
373 1 EZUSB_IRQ_CLEAR();
374 1 USBIRQ = bmSUTOK; // Clear SUTOK IRQ
375 1 }
376
377 void ISR_Sof(void) interrupt 0
378 {
379 1 EZUSB_IRQ_CLEAR();
380 1 USBIRQ = bmSOF; // Clear SOF IRQ
381 1 }
382
383 void ISR_Ures(void) interrupt 0
384 {
385 1 // whenever we get a USB reset, we should revert to full speed mode
386 1 pConfigDscr = pFullSpeedConfigDscr;
387 1 ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
388 1 pOtherConfigDscr = pHighSpeedConfigDscr;
389 1 ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
390 1
391 1 EZUSB_IRQ_CLEAR();
392 1 USBIRQ = bmURES; // Clear URES IRQ
393 1 }
394
395 void ISR_Susp(void) interrupt 0
396 {
397 1 Sleep = TRUE;
398 1 EZUSB_IRQ_CLEAR();
399 1 USBIRQ = bmSUSP;
400 1 }
401
402 void ISR_Highspeed(void) interrupt 0
403 {
404 1 if (EZUSB_HIGHSPEED())
405 1 {
406 2 pConfigDscr = pHighSpeedConfigDscr;
407 2 ((CONFIGDSCR xdata *) pConfigDscr)->type = CONFIG_DSCR;
408 2 pOtherConfigDscr = pFullSpeedConfigDscr;
409 2 ((CONFIGDSCR xdata *) pOtherConfigDscr)->type = OTHERSPEED_DSCR;
410 2 }
411 1
412 1 EZUSB_IRQ_CLEAR();
413 1 USBIRQ = bmHSGRANT;
414 1 }
415 void ISR_Ep0ack(void) interrupt 0
416 {
417 1 }
418 void ISR_Stub(void) interrupt 0
419 {
420 1 }
421 void ISR_Ep0in(void) interrupt 0
422 {
423 1 }
424 void ISR_Ep0out(void) interrupt 0
C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 8
425 {
426 1 }
427 void ISR_Ep1in(void) interrupt 0
428 {
429 1 }
430 void ISR_Ep1out(void) interrupt 0
431 {
432 1 }
433 void ISR_Ep2inout(void) interrupt 0
434 {
435 1 }
436 void ISR_Ep4inout(void) interrupt 0
437 {
438 1 }
439 void ISR_Ep6inout(void) interrupt 0
440 {
441 1 }
442 void ISR_Ep8inout(void) interrupt 0
443 {
444 1 }
445 void ISR_Ibn(void) interrupt 0
446 {
447 1 }
448 void ISR_Ep0pingnak(void) interrupt 0
449 {
450 1 }
451 void ISR_Ep1pingnak(void) interrupt 0
452 {
453 1 }
454 void ISR_Ep2pingnak(void) interrupt 0
455 {
456 1 }
457 void ISR_Ep4pingnak(void) interrupt 0
458 {
459 1 }
460 void ISR_Ep6pingnak(void) interrupt 0
461 {
462 1 }
463 void ISR_Ep8pingnak(void) interrupt 0
464 {
465 1 }
466 void ISR_Errorlimit(void) interrupt 0
467 {
468 1 }
469 void ISR_Ep2piderror(void) interrupt 0
470 {
471 1 }
472 void ISR_Ep4piderror(void) interrupt 0
473 {
474 1 }
475 void ISR_Ep6piderror(void) interrupt 0
476 {
477 1 }
478 void ISR_Ep8piderror(void) interrupt 0
479 {
480 1 }
481 void ISR_Ep2pflag(void) interrupt 0
482 {
483 1 }
484 void ISR_Ep4pflag(void) interrupt 0
485 {
486 1 }
C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 9
487 void ISR_Ep6pflag(void) interrupt 0
488 {
489 1 }
490 void ISR_Ep8pflag(void) interrupt 0
491 {
492 1 }
493 void ISR_Ep2eflag(void) interrupt 0
494 {
495 1 }
496 void ISR_Ep4eflag(void) interrupt 0
497 {
498 1 }
499 void ISR_Ep6eflag(void) interrupt 0
500 {
501 1 }
502 void ISR_Ep8eflag(void) interrupt 0
503 {
504 1 }
505 void ISR_Ep2fflag(void) interrupt 0
506 {
507 1 }
508 void ISR_Ep4fflag(void) interrupt 0
509 {
510 1 }
511 void ISR_Ep6fflag(void) interrupt 0
512 {
513 1 }
514 void ISR_Ep8fflag(void) interrupt 0
515 {
516 1 }
517 void ISR_GpifComplete(void) interrupt 0
518 {
519 1 }
520 void ISR_GpifWaveform(void) interrupt 0
521 {
522 1 }
523 /*
524 void Setup_FLOWSTATE_Read ( void )
525 {
526 FLOWSTATE = FlowStates[18]; // 1000 0011b - FSE=1, FS[2:0]=003
527 SYNCDELAY;
528 FLOWEQ0CTL = FlowStates[20]; // CTL1/CTL2 = 0 when flow condition equals zero (data flows)
529 SYNCDELAY;
530 FLOWEQ1CTL = FlowStates[21]; // CTL1/CTL2 = 1 when flow condition equals one (data does not flow)
531 SYNCDELAY;
532 }
533
534 void Setup_FLOWSTATE_Write ( void )
535 {
536 FLOWSTATE = FlowStates[27]; // 1000 0001b - FSE=1, FS[2:0]=001
537 SYNCDELAY;
538 FLOWEQ0CTL = FlowStates[29]; // CTL0 = 0 when flow condition equals zero (data flows)
539 SYNCDELAY;
540 FLOWEQ1CTL = FlowStates[30]; // CTL0 = 1 when flow condition equals one (data does not flow)
541 SYNCDELAY;
542 }
543 */
MODULE INFORMATION: STATIC OVERLAYABLE
CODE SIZE = 789 ----
CONSTANT SIZE = ---- ----
C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 10
XDATA SIZE = 2 ----
PDATA SIZE = ---- ----
DATA SIZE = 4 ----
IDATA SIZE = ---- ----
BIT SIZE = 2 ----
END OF MODULE INFORMATION.
C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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