📄 fx2_to_extsyncfifo.lst
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C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE FX2_TO_EXTSYNCFIFO
OBJECT MODULE PLACED IN FX2_to_extsyncFIFO.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE FX2_to_extsyncFIFO.c DEBUG OBJECTEXTEND
line level source
1 #pragma NOIV // Do not generate interrupt vectors
2 //-----------------------------------------------------------------------------
3 // File: FX2_to_extsyncFIFO.c
4 // Contents: Hooks required to implement FX2 GPIF to external sync. FIFO
5 // interface using CY4265-15AC
6 //
7 // Copyright (c) 2003 Cypress Semiconductor, Inc. All rights reserved
8 //-----------------------------------------------------------------------------
9 #include "fx2.h"
10 #include "fx2regs.h"
11 #include "fx2sdly.h" // SYNCDELAY macro, see Section 15.14 of FX2 Tech.
12 // Ref. Manual for usage details.
13
14 #define EXTFIFONOTFULL GPIFREADYSTAT & bmBIT1
15 #define EXTFIFONOTEMPTY GPIFREADYSTAT & bmBIT0
16
17 #define GPIFTRIGRD 4
18
19 #define GPIF_EP2 0
20 #define GPIF_EP4 1
21 #define GPIF_EP6 2
22 #define GPIF_EP8 3
23
24
25 extern BOOL GotSUD; // Received setup data flag
26 extern BOOL Sleep;
27 extern BOOL Rwuen;
28 extern BOOL Selfpwr;
29
30 BYTE Configuration; // Current configuration
31 BYTE AlternateSetting; // Alternate settings
32 BOOL in_enable = FALSE; // flag to enable IN transfers
33 BOOL enum_high_speed = FALSE; // flag to let firmware know FX2 enumerated at high speed
34 static WORD xdata Tcount = 0; // transaction count
35 static WORD xFIFOBC_IN = 0x0000; // variable that contains EP6FIFOBCH/L value
36
37 //-----------------------------------------------------------------------------
38 // Task Dispatcher hooks
39 // The following hooks are called by the task dispatcher.
40 //-----------------------------------------------------------------------------
41 //void Setup_FLOWSTATE_Write ( void );
42 //void Setup_FLOWSTATE_Read ( void );
43 void GpifInit ();
44
45 void TD_Init(void) // Called once at startup
46 {
47 1 // set the CPU clock to 48MHz
48 1 CPUCS = ((CPUCS & ~bmCLKSPD) | bmCLKSPD1);
49 1 SYNCDELAY;
50 1
51 1 EP2CFG = 0xA0; // EP2OUT, bulk, size 512, 4x buffered
52 1 SYNCDELAY;
53 1 EP4CFG = 0x00; // EP4 not valid
54 1 SYNCDELAY;
55 1 EP6CFG = 0xE0; // EP6IN, bulk, size 512, 4x buffered
C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 2
56 1 SYNCDELAY;
57 1 EP8CFG = 0x00; // EP8 not valid
58 1 SYNCDELAY;
59 1
60 1
61 1 FIFORESET = 0x80; // set NAKALL bit to NAK all transfers from host
62 1 SYNCDELAY;
63 1 FIFORESET = 0x02; // reset EP2 FIFO
64 1 SYNCDELAY;
65 1 FIFORESET = 0x06; // reset EP6 FIFO
66 1 SYNCDELAY;
67 1 FIFORESET = 0x00; // clear NAKALL bit to resume normal operation
68 1 SYNCDELAY;
69 1
70 1 EP2FIFOCFG = 0x01; // allow core to see zero to one transition of auto out bit
71 1 SYNCDELAY;
72 1 EP2FIFOCFG = 0x11; // auto out mode, disable PKTEND zero length send, word ops
73 1 SYNCDELAY;
74 1 EP6FIFOCFG = 0x09; // auto in mode, disable PKTEND zero length send, word ops
75 1 SYNCDELAY;
76 1
77 1 GpifInit (); // initialize GPIF registers
78 1
79 1
80 1 SYNCDELAY;
81 1 EP2GPIFFLGSEL = 0x01; // For EP2OUT, GPIF uses EF flag
82 1 SYNCDELAY;
83 1 EP6GPIFFLGSEL = 0x02; // For EP6IN, GPIF uses FF flag
84 1 SYNCDELAY;
85 1
86 1 }
87
88 void TD_Poll(void)
89 {
90 1 if( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
91 1 {
92 2 if ( ! ( EP24FIFOFLGS & 0x02 ) ) // if there's a packet in the peripheral domain for EP2
93 2 {
94 3 if ( EXTFIFONOTFULL ) // if the external FIFO is not full
95 3 {
96 4
97 4 if(enum_high_speed)
98 4 {
99 5 SYNCDELAY;
100 5 GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x010
-0)
101 5 SYNCDELAY;
102 5 GPIFTCB0 = 0x00;
103 5 SYNCDELAY;
104 5 }
105 4 else
106 4 {
107 5 SYNCDELAY;
108 5 GPIFTCB1 = 0x00; // setup transaction count (64 bytes/2 for word wide -> 0x20)
109 5 SYNCDELAY;
110 5 GPIFTCB0 = 0x20;
111 5 SYNCDELAY;
112 5 }
113 4
114 4 // trigger FIFO write transaction(s), using SFR
115 4
116 4 SYNCDELAY;
C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 3
117 4 GPIFTRIG = GPIF_EP2; // launch GPIF FIFO WRITE Transaction from EP2 FIFO
118 4 SYNCDELAY;
119 4
120 4 SYNCDELAY;
121 4 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
122 4 {
123 5 ;
124 5 }
125 4
126 4 SYNCDELAY;
127 4 }
128 3 }
129 2 }
130 1
131 1 if(in_enable) // if IN transfers are enabled
132 1 {
133 2 if ( GPIFTRIG & 0x80 ) // if GPIF interface IDLE
134 2 {
135 3 if ( EXTFIFONOTEMPTY ) // if external FIFO is not empty
136 3 {
137 4 if ( !( EP68FIFOFLGS & 0x01 ) ) // if EP6 FIFO is not full
138 4 {
139 5 if(enum_high_speed)
140 5 {
141 6 SYNCDELAY;
142 6 GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x010
-0)
143 6 SYNCDELAY;
144 6 GPIFTCB0 = 0x00;
145 6 SYNCDELAY;
146 6 }
147 5 else
148 5 {
149 6 SYNCDELAY;
150 6 GPIFTCB1 = 0x01; // setup transaction count (512 bytes/2 for word wide -> 0x010
-0)
151 6 SYNCDELAY;
152 6 GPIFTCB0 = 0x00;
153 6 SYNCDELAY;
154 6 }
155 5
156 5 GPIFTRIG = GPIFTRIGRD | GPIF_EP6; // launch GPIF FIFO READ Transaction to EP6 FIFO
157 5 SYNCDELAY;
158 5
159 5 while( !( GPIFTRIG & 0x80 ) ) // poll GPIFTRIG.7 GPIF Done bit
160 5 {
161 6 ;
162 6 }
163 5
164 5 SYNCDELAY;
165 5 }
166 4 }
167 3 }
168 2 }
169 1
170 1 }
171
172 BOOL TD_Suspend(void) // Called before the device goes into suspend mode
173 {
174 1 return(TRUE);
175 1 }
176
C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 4
177 BOOL TD_Resume(void) // Called after the device resumes
178 {
179 1 return(TRUE);
180 1 }
181
182 //-----------------------------------------------------------------------------
183 // Device Request hooks
184 // The following hooks are called by the end point 0 device request parser.
185 //-----------------------------------------------------------------------------
186
187 BOOL DR_GetDescriptor(void)
188 {
189 1 return(TRUE);
190 1 }
191
192 BOOL DR_SetConfiguration(void) // Called when a Set Configuration command is received
193 {
194 1 if( EZUSB_HIGHSPEED( ) )
195 1 { // FX2 enumerated at high speed
196 2 SYNCDELAY; //
197 2 EP6AUTOINLENH = 0x02; // set AUTOIN commit length to 512 bytes
198 2 SYNCDELAY; //
199 2 EP6AUTOINLENL = 0x00;
200 2 SYNCDELAY;
201 2 enum_high_speed = TRUE;
202 2 }
203 1 else
204 1 { // FX2 enumerated at full speed
205 2 SYNCDELAY;
206 2 EP6AUTOINLENH = 0x00; // set AUTOIN commit length to 64 bytes
207 2 SYNCDELAY;
208 2 EP6AUTOINLENL = 0x40;
209 2 SYNCDELAY;
210 2 enum_high_speed = FALSE;
211 2 }
212 1
213 1 Configuration = SETUPDAT[2];
214 1 return(TRUE); // Handled by user code
215 1 }
216
217 BOOL DR_GetConfiguration(void) // Called when a Get Configuration command is received
218 {
219 1 EP0BUF[0] = Configuration;
220 1 EP0BCH = 0;
221 1 EP0BCL = 1;
222 1 return(TRUE); // Handled by user code
223 1 }
224
225 BOOL DR_SetInterface(void) // Called when a Set Interface command is received
226 {
227 1 AlternateSetting = SETUPDAT[2];
228 1 return(TRUE); // Handled by user code
229 1 }
230
231 BOOL DR_GetInterface(void) // Called when a Set Interface command is received
232 {
233 1 EP0BUF[0] = AlternateSetting;
234 1 EP0BCH = 0;
235 1 EP0BCL = 1;
236 1 return(TRUE); // Handled by user code
237 1 }
238
C51 COMPILER V7.50 FX2_TO_EXTSYNCFIFO 07/09/2007 19:43:29 PAGE 5
239 BOOL DR_GetStatus(void)
240 {
241 1 return(TRUE);
242 1 }
243
244 BOOL DR_ClearFeature(void)
245 {
246 1 return(TRUE);
247 1 }
248
249 BOOL DR_SetFeature(void)
250 {
251 1 return(TRUE);
252 1 }
253
254 #define VX_B2 0xB2 // reset the external FIFO
255 #define VX_B3 0xB3 // enable IN transfers
256 #define VX_B4 0xB4 // disable IN transfers
257 #define VX_B5 0xB5 // read GPIFREADYSTAT register
258 #define VX_B6 0xB6 // read GPIFTRIG register
259
260 //SLAVE FIFO 通道选择命令
261 //保留跟SLAVE FIFO在VC中使用的读写函数一样而保留的，其实在这只有VX_BB有用
262 #define VX_BA 0xBA // EP2 OUT
263 #define VX_BB 0xBB // EP6 IN
264
265 BOOL DR_VendorCmnd(void)
266 {
267 1 switch (SETUPDAT[1])
268 1 {
269 2 case VX_B2:
270 2 {
271 3 // reset the external FIFO
272 3 /*
273 3 OEA |= 0x04; // turn on PA2 as output pin
274 3 IOA |= 0x04; // pull PA2 high initially
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