usb_fpga.fit.eqn

ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序

C1_q_b[2]_PORT_B_address_reg = DFFE(C1_q_b[2]_PORT_B_address, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_PORT_A_write_enable = VCC;
C1_q_b[2]_PORT_A_write_enable_reg = DFFE(C1_q_b[2]_PORT_A_write_enable, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_read_enable = VCC;
C1_q_b[2]_PORT_B_read_enable_reg = DFFE(C1_q_b[2]_PORT_B_read_enable, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_clock_0 = GLOBAL(gclk);
C1_q_b[2]_clock_1 = GLOBAL(gclk);
C1_q_b[2]_clock_enable_0 = A1L114;
C1_q_b[2]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[2]_PORT_B_data_out = MEMORY(C1_q_b[2]_PORT_A_data_in_reg, , C1_q_b[2]_PORT_A_address_reg, C1_q_b[2]_PORT_B_address_reg, C1_q_b[2]_PORT_A_write_enable_reg, C1_q_b[2]_PORT_B_read_enable_reg, , , C1_q_b[2]_clock_0, C1_q_b[2]_clock_1, C1_q_b[2]_clock_enable_0, C1_q_b[2]_clock_enable_1, , );
C1_q_b[2] = C1_q_b[2]_PORT_B_data_out[0];

--C1_q_b[13] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[13] at M4K_X17_Y15
C1_q_b[2]_PORT_A_data_in = BUS(A1L176, A1L197, A1L206, A1L209);
C1_q_b[2]_PORT_A_data_in_reg = DFFE(C1_q_b[2]_PORT_A_data_in, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[2]_PORT_A_address_reg = DFFE(C1_q_b[2]_PORT_A_address, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[2]_PORT_B_address_reg = DFFE(C1_q_b[2]_PORT_B_address, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_PORT_A_write_enable = VCC;
C1_q_b[2]_PORT_A_write_enable_reg = DFFE(C1_q_b[2]_PORT_A_write_enable, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_read_enable = VCC;
C1_q_b[2]_PORT_B_read_enable_reg = DFFE(C1_q_b[2]_PORT_B_read_enable, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_clock_0 = GLOBAL(gclk);
C1_q_b[2]_clock_1 = GLOBAL(gclk);
C1_q_b[2]_clock_enable_0 = A1L114;
C1_q_b[2]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[2]_PORT_B_data_out = MEMORY(C1_q_b[2]_PORT_A_data_in_reg, , C1_q_b[2]_PORT_A_address_reg, C1_q_b[2]_PORT_B_address_reg, C1_q_b[2]_PORT_A_write_enable_reg, C1_q_b[2]_PORT_B_read_enable_reg, , , C1_q_b[2]_clock_0, C1_q_b[2]_clock_1, C1_q_b[2]_clock_enable_0, C1_q_b[2]_clock_enable_1, , );
C1_q_b[13] = C1_q_b[2]_PORT_B_data_out[3];

--C1_q_b[12] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[12] at M4K_X17_Y15
C1_q_b[2]_PORT_A_data_in = BUS(A1L176, A1L197, A1L206, A1L209);
C1_q_b[2]_PORT_A_data_in_reg = DFFE(C1_q_b[2]_PORT_A_data_in, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[2]_PORT_A_address_reg = DFFE(C1_q_b[2]_PORT_A_address, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[2]_PORT_B_address_reg = DFFE(C1_q_b[2]_PORT_B_address, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_PORT_A_write_enable = VCC;
C1_q_b[2]_PORT_A_write_enable_reg = DFFE(C1_q_b[2]_PORT_A_write_enable, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_read_enable = VCC;
C1_q_b[2]_PORT_B_read_enable_reg = DFFE(C1_q_b[2]_PORT_B_read_enable, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_clock_0 = GLOBAL(gclk);
C1_q_b[2]_clock_1 = GLOBAL(gclk);
C1_q_b[2]_clock_enable_0 = A1L114;
C1_q_b[2]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[2]_PORT_B_data_out = MEMORY(C1_q_b[2]_PORT_A_data_in_reg, , C1_q_b[2]_PORT_A_address_reg, C1_q_b[2]_PORT_B_address_reg, C1_q_b[2]_PORT_A_write_enable_reg, C1_q_b[2]_PORT_B_read_enable_reg, , , C1_q_b[2]_clock_0, C1_q_b[2]_clock_1, C1_q_b[2]_clock_enable_0, C1_q_b[2]_clock_enable_1, , );
C1_q_b[12] = C1_q_b[2]_PORT_B_data_out[2];

--C1_q_b[9] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[9] at M4K_X17_Y15
C1_q_b[2]_PORT_A_data_in = BUS(A1L176, A1L197, A1L206, A1L209);
C1_q_b[2]_PORT_A_data_in_reg = DFFE(C1_q_b[2]_PORT_A_data_in, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[2]_PORT_A_address_reg = DFFE(C1_q_b[2]_PORT_A_address, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[2]_PORT_B_address_reg = DFFE(C1_q_b[2]_PORT_B_address, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_PORT_A_write_enable = VCC;
C1_q_b[2]_PORT_A_write_enable_reg = DFFE(C1_q_b[2]_PORT_A_write_enable, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_read_enable = VCC;
C1_q_b[2]_PORT_B_read_enable_reg = DFFE(C1_q_b[2]_PORT_B_read_enable, C1_q_b[2]_clock_1, , , C1_q_b[2]_clock_enable_1);
C1_q_b[2]_clock_0 = GLOBAL(gclk);
C1_q_b[2]_clock_1 = GLOBAL(gclk);
C1_q_b[2]_clock_enable_0 = A1L114;
C1_q_b[2]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[2]_PORT_B_data_out = MEMORY(C1_q_b[2]_PORT_A_data_in_reg, , C1_q_b[2]_PORT_A_address_reg, C1_q_b[2]_PORT_B_address_reg, C1_q_b[2]_PORT_A_write_enable_reg, C1_q_b[2]_PORT_B_read_enable_reg, , , C1_q_b[2]_clock_0, C1_q_b[2]_clock_1, C1_q_b[2]_clock_enable_0, C1_q_b[2]_clock_enable_1, , );
C1_q_b[9] = C1_q_b[2]_PORT_B_data_out[1];


--A1L100Q is fifomemory~8 at LC_X19_Y16_N1
--operation mode is normal

A1L100Q_lut_out = A1L176;
A1L100Q = DFFEAS(A1L100Q_lut_out, GLOBAL(gclk), VCC, , A1L118, , , , );


--A1L101Q is fifomemory~10 at LC_X19_Y16_N6
--operation mode is normal

A1L101Q_lut_out = A1L179;
A1L101Q = DFFEAS(A1L101Q_lut_out, GLOBAL(gclk), VCC, , A1L118, , , , );


--A1L102Q is fifomemory~12 at LC_X19_Y16_N9
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L102Q_lut_out = GND;
A1L102Q = DFFEAS(A1L102Q_lut_out, GLOBAL(gclk), VCC, , A1L118, A1L182, , , VCC);


--A1L103Q is fifomemory~14 at LC_X19_Y19_N6
--operation mode is normal

A1L103Q_lut_out = A1L185;
A1L103Q = DFFEAS(A1L103Q_lut_out, GLOBAL(gclk), VCC, , A1L118, , , , );


--A1L104Q is fifomemory~16 at LC_X19_Y18_N4
--operation mode is normal

A1L104Q_lut_out = A1L188;
A1L104Q = DFFEAS(A1L104Q_lut_out, GLOBAL(gclk), VCC, , A1L118, , , , );


--A1L105Q is fifomemory~18 at LC_X19_Y18_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L105Q_lut_out = GND;
A1L105Q = DFFEAS(A1L105Q_lut_out, GLOBAL(gclk), VCC, , A1L118, A1L191, , , VCC);


--A1L106Q is fifomemory~20 at LC_X19_Y18_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L106Q_lut_out = GND;
A1L106Q = DFFEAS(A1L106Q_lut_out, GLOBAL(gclk), VCC, , A1L118, A1L194, , , VCC);


--A1L107Q is fifomemory~22 at LC_X19_Y17_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L107Q_lut_out = GND;
A1L107Q = DFFEAS(A1L107Q_lut_out, GLOBAL(gclk), VCC, , A1L118, A1L197, , , VCC);


--C1_q_b[10] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[10] at M4K_X17_Y17
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[10]_PORT_A_data_in = BUS(A1L200, A1L203, A1L212, A1L215);
C1_q_b[10]_PORT_A_data_in_reg = DFFE(C1_q_b[10]_PORT_A_data_in, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[10]_PORT_A_address_reg = DFFE(C1_q_b[10]_PORT_A_address, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[10]_PORT_B_address_reg = DFFE(C1_q_b[10]_PORT_B_address, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_PORT_A_write_enable = VCC;
C1_q_b[10]_PORT_A_write_enable_reg = DFFE(C1_q_b[10]_PORT_A_write_enable, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_read_enable = VCC;
C1_q_b[10]_PORT_B_read_enable_reg = DFFE(C1_q_b[10]_PORT_B_read_enable, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_clock_0 = GLOBAL(gclk);
C1_q_b[10]_clock_1 = GLOBAL(gclk);
C1_q_b[10]_clock_enable_0 = A1L114;
C1_q_b[10]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[10]_PORT_B_data_out = MEMORY(C1_q_b[10]_PORT_A_data_in_reg, , C1_q_b[10]_PORT_A_address_reg, C1_q_b[10]_PORT_B_address_reg, C1_q_b[10]_PORT_A_write_enable_reg, C1_q_b[10]_PORT_B_read_enable_reg, , , C1_q_b[10]_clock_0, C1_q_b[10]_clock_1, C1_q_b[10]_clock_enable_0, C1_q_b[10]_clock_enable_1, , );
C1_q_b[10] = C1_q_b[10]_PORT_B_data_out[0];

--C1_q_b[15] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[15] at M4K_X17_Y17
C1_q_b[10]_PORT_A_data_in = BUS(A1L200, A1L203, A1L212, A1L215);
C1_q_b[10]_PORT_A_data_in_reg = DFFE(C1_q_b[10]_PORT_A_data_in, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[10]_PORT_A_address_reg = DFFE(C1_q_b[10]_PORT_A_address, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[10]_PORT_B_address_reg = DFFE(C1_q_b[10]_PORT_B_address, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_PORT_A_write_enable = VCC;
C1_q_b[10]_PORT_A_write_enable_reg = DFFE(C1_q_b[10]_PORT_A_write_enable, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_read_enable = VCC;
C1_q_b[10]_PORT_B_read_enable_reg = DFFE(C1_q_b[10]_PORT_B_read_enable, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_clock_0 = GLOBAL(gclk);
C1_q_b[10]_clock_1 = GLOBAL(gclk);
C1_q_b[10]_clock_enable_0 = A1L114;
C1_q_b[10]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[10]_PORT_B_data_out = MEMORY(C1_q_b[10]_PORT_A_data_in_reg, , C1_q_b[10]_PORT_A_address_reg, C1_q_b[10]_PORT_B_address_reg, C1_q_b[10]_PORT_A_write_enable_reg, C1_q_b[10]_PORT_B_read_enable_reg, , , C1_q_b[10]_clock_0, C1_q_b[10]_clock_1, C1_q_b[10]_clock_enable_0, C1_q_b[10]_clock_enable_1, , );
C1_q_b[15] = C1_q_b[10]_PORT_B_data_out[3];

--C1_q_b[14] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[14] at M4K_X17_Y17
C1_q_b[10]_PORT_A_data_in = BUS(A1L200, A1L203, A1L212, A1L215);
C1_q_b[10]_PORT_A_data_in_reg = DFFE(C1_q_b[10]_PORT_A_data_in, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[10]_PORT_A_address_reg = DFFE(C1_q_b[10]_PORT_A_address, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[10]_PORT_B_address_reg = DFFE(C1_q_b[10]_PORT_B_address, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_PORT_A_write_enable = VCC;
C1_q_b[10]_PORT_A_write_enable_reg = DFFE(C1_q_b[10]_PORT_A_write_enable, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_read_enable = VCC;
C1_q_b[10]_PORT_B_read_enable_reg = DFFE(C1_q_b[10]_PORT_B_read_enable, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_clock_0 = GLOBAL(gclk);
C1_q_b[10]_clock_1 = GLOBAL(gclk);
C1_q_b[10]_clock_enable_0 = A1L114;
C1_q_b[10]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[10]_PORT_B_data_out = MEMORY(C1_q_b[10]_PORT_A_data_in_reg, , C1_q_b[10]_PORT_A_address_reg, C1_q_b[10]_PORT_B_address_reg, C1_q_b[10]_PORT_A_write_enable_reg, C1_q_b[10]_PORT_B_read_enable_reg, , , C1_q_b[10]_clock_0, C1_q_b[10]_clock_1, C1_q_b[10]_clock_enable_0, C1_q_b[10]_clock_enable_1, , );
C1_q_b[14] = C1_q_b[10]_PORT_B_data_out[2];

--C1_q_b[11] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[11] at M4K_X17_Y17
C1_q_b[10]_PORT_A_data_in = BUS(A1L200, A1L203, A1L212, A1L215);
C1_q_b[10]_PORT_A_data_in_reg = DFFE(C1_q_b[10]_PORT_A_data_in, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[10]_PORT_A_address_reg = DFFE(C1_q_b[10]_PORT_A_address, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[10]_PORT_B_address_reg = DFFE(C1_q_b[10]_PORT_B_address, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_PORT_A_write_enable = VCC;
C1_q_b[10]_PORT_A_write_enable_reg = DFFE(C1_q_b[10]_PORT_A_write_enable, C1_q_b[10]_clock_0, , , C1_q_b[10]_clock_enable_0);
C1_q_b[10]_PORT_B_read_enable = VCC;
C1_q_b[10]_PORT_B_read_enable_reg = DFFE(C1_q_b[10]_PORT_B_read_enable, C1_q_b[10]_clock_1, , , C1_q_b[10]_clock_enable_1);
C1_q_b[10]_clock_0 = GLOBAL(gclk);
C1_q_b[10]_clock_1 = GLOBAL(gclk);
C1_q_b[10]_clock_enable_0 = A1L114;
C1_q_b[10]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[10]_PORT_B_data_out = MEMORY(C1_q_b[10]_PORT_A_data_in_reg, , C1_q_b[10]_PORT_A_address_reg, C1_q_b[10]_PORT_B_address_reg, C1_q_b[10]_PORT_A_write_enable_reg, C1_q_b[10]_PORT_B_read_enable_reg, , , C1_q_b[10]_clock_0, C1_q_b[10]_clock_1, C1_q_b[10]_clock_enable_0, C1_q_b[10]_clock_enable_1, , );
C1_q_b[11] = C1_q_b[10]_PORT_B_data_out[1];


--A1L108Q is fifomemory~24 at LC_X19_Y17_N6
--operation mode is normal

A1L108Q_lut_out = A1L200;
A1L108Q = DFFEAS(A1L108Q_lut_out, GLOBAL(gclk), VCC, , A1L118, , , , );


--A1L109Q is fifomemory~26 at LC_X19_Y17_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L109Q_lut_out = GND;
A1L109Q = DFFEAS(A1L109Q_lut_out, GLOBAL(gclk), VCC, , A1L118, A1L203, , , VCC);


--A1L110Q is fifomemory~28 at LC_X19_Y17_N8
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L110Q_lut_out = GND;
A1L110Q = DFFEAS(A1L110Q_lut_out, GLOBAL(gclk), VCC, , A1L118, A1L206, , , VCC);


--A1L111Q is fifomemory~30 at LC_X19_Y17_N3
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L111Q_lut_out = GND;
A1L111Q = DFFEAS(A1L111Q_lut_out, GLOBAL(gclk), VCC, , A1L118, A1L209, , , VCC);


--A1L112Q is fifomemory~32 at LC_X19_Y19_N5
--operation mode is normal

A1L112Q_lut_out = A1L212;
A1L112Q = DFFEAS(A1L112Q_lut_out, GLOBAL(gclk), VCC, , A1L118, , , , );


--A1L113Q is fifomemory~34 at LC_X19_Y19_N2
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L113Q_lut_out = GND;
A1L113Q = DFFEAS(A1L113Q_lut_out, GLOBAL(gclk), VCC, , A1L118, A1L215, , , VCC);


--A1L243 is LessThan~435 at LC_X21_Y14_N4
--operation mode is arithmetic

A1L243 = CARRY(fifowraddr[4] & (!A1L246 # !fifordaddr[4]) # !fifowraddr[4] & !fifordaddr[4] & !A1L246);


--A1L114 is fifomemory~309 at LC_X21_Y16_N9
--operation mode is normal

A1L114 = RESETFPGA & !CTL0_FLAGA;


--A1L115 is fifomemory~310 at LC_X19_Y16_N8
--operation mode is normal

A1L115 = !fifowraddr[7] & !fifowraddr[9];


--A1L116 is fifomemory~311 at LC_X19_Y16_N2
--operation mode is normal

A1L116 = !fifowraddr[1] & !fifowraddr[0] & !fifowraddr[5] & !fifowraddr[3];


--A1L117 is fifomemory~312 at LC_X19_Y16_N3
--operation mode is normal

A1L117 = !fifowraddr[6] & !fifowraddr[4] & !fifowraddr[2] & !fifowraddr[8];


--A1L118 is fifomemory~313 at LC_X19_Y16_N4
--operation mode is normal

A1L118 = A1L114 & A1L115 & A1L116 & A1L117;


--A1L245 is LessThan~440 at LC_X21_Y14_N3
--operation mode is arithmetic

A1L245_cout_0 = fifordaddr[3] & (!A1L248 # !fifowraddr[3]) # !fifordaddr[3] & !fifowraddr[3] & !A1L248;
A1L245 = CARRY(A1L245_cout_0);

--A1L246 is LessThan~440COUT1_462 at LC_X21_Y14_N3
--operation mode is arithmetic

A1L246_cout_1 = fifordaddr[3] & (!A1L249 # !fifowraddr[3]) # !fifordaddr[3] & !fifowraddr[3] & !A1L249;
A1L246 = CARRY(A1L246_cout_1);


--A1L248 is LessThan~445 at LC_X21_Y14_N2
--operation mode is arithmetic

A1L248_cout_0 = fifowraddr[2] & (!A1L251 # !fifordaddr[2]) # !fifowraddr[2] & !fifordaddr[2] & !A1L251;
A1L248 = CARRY(A1L248_cout_0);

--A1L249 is LessThan~445COUT1_461 at LC_X21_Y14_N2
--operation mode is arithmetic

A1L249_cout_1 = fifowraddr[2] & (!A1L252 # !fifordaddr[2]) # !fifowraddr[2] & !fifordaddr[2] & !A1L252;
A1L249 = CARRY(A1L249_cout_1);


--A1L251 is LessThan~450 at LC_X21_Y14_N1
--operation mode is arithmetic

A1L251_cout_0 = fifowraddr[1] & fifordaddr[1] & !A1L254 # !fifowraddr[1] & (fifordaddr[1] # !A1L254);
A1L251 = CARRY(A1L251_cout_0);

--A1L252 is LessThan~450COUT1_460 at LC_X21_Y14_N1
--operation mode is arithmetic

A