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📄 usb_fpga.fit.eqn

📁 ＥＺ－ＵＳＢ控制器６８０１３ＧＰＩＦ－ＦＩＦＯ读写的Ｃ语言程序
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--A1L238 is LessThan~425COUT1_464 at LC_X21_Y14_N6
--operation mode is arithmetic

A1L238_cout_1 = fifowraddr[6] & (!A1L241 # !fifordaddr[6]) # !fifowraddr[6] & !fifordaddr[6] & !A1L241;
A1L238 = CARRY(A1L238_cout_1);


--data2usb[0] is data2usb[0] at LC_X19_Y16_N7
--operation mode is normal

data2usb[0]_lut_out = A1L97Q & (C1_q_b[0]) # !A1L97Q & A1L98Q;
data2usb[0] = DFFEAS(data2usb[0]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[1] is data2usb[1] at LC_X16_Y16_N8
--operation mode is normal

data2usb[1]_lut_out = A1L97Q & (C1_q_b[1]) # !A1L97Q & A1L99Q;
data2usb[1] = DFFEAS(data2usb[1]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[2] is data2usb[2] at LC_X16_Y16_N3
--operation mode is normal

data2usb[2]_lut_out = A1L97Q & C1_q_b[2] # !A1L97Q & (A1L100Q);
data2usb[2] = DFFEAS(data2usb[2]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[3] is data2usb[3] at LC_X16_Y16_N0
--operation mode is normal

data2usb[3]_lut_out = A1L97Q & C1_q_b[3] # !A1L97Q & (A1L101Q);
data2usb[3] = DFFEAS(data2usb[3]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[4] is data2usb[4] at LC_X16_Y16_N6
--operation mode is normal

data2usb[4]_lut_out = A1L97Q & C1_q_b[4] # !A1L97Q & (A1L102Q);
data2usb[4] = DFFEAS(data2usb[4]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[5] is data2usb[5] at LC_X16_Y16_N7
--operation mode is normal

data2usb[5]_lut_out = A1L97Q & (C1_q_b[5]) # !A1L97Q & A1L103Q;
data2usb[5] = DFFEAS(data2usb[5]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[6] is data2usb[6] at LC_X19_Y18_N9
--operation mode is normal

data2usb[6]_lut_out = A1L97Q & C1_q_b[6] # !A1L97Q & (A1L104Q);
data2usb[6] = DFFEAS(data2usb[6]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[7] is data2usb[7] at LC_X19_Y18_N5
--operation mode is normal

data2usb[7]_lut_out = A1L97Q & C1_q_b[7] # !A1L97Q & (A1L105Q);
data2usb[7] = DFFEAS(data2usb[7]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[8] is data2usb[8] at LC_X19_Y18_N0
--operation mode is normal

data2usb[8]_lut_out = A1L97Q & (C1_q_b[8]) # !A1L97Q & A1L106Q;
data2usb[8] = DFFEAS(data2usb[8]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[9] is data2usb[9] at LC_X19_Y17_N1
--operation mode is normal

data2usb[9]_lut_out = A1L97Q & (C1_q_b[9]) # !A1L97Q & A1L107Q;
data2usb[9] = DFFEAS(data2usb[9]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[10] is data2usb[10] at LC_X19_Y17_N2
--operation mode is normal

data2usb[10]_lut_out = A1L97Q & (C1_q_b[10]) # !A1L97Q & (A1L108Q);
data2usb[10] = DFFEAS(data2usb[10]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[11] is data2usb[11] at LC_X19_Y17_N0
--operation mode is normal

data2usb[11]_lut_out = A1L97Q & (C1_q_b[11]) # !A1L97Q & A1L109Q;
data2usb[11] = DFFEAS(data2usb[11]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[12] is data2usb[12] at LC_X19_Y17_N7
--operation mode is normal

data2usb[12]_lut_out = A1L97Q & (C1_q_b[12]) # !A1L97Q & A1L110Q;
data2usb[12] = DFFEAS(data2usb[12]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[13] is data2usb[13] at LC_X19_Y17_N9
--operation mode is normal

data2usb[13]_lut_out = A1L97Q & (C1_q_b[13]) # !A1L97Q & A1L111Q;
data2usb[13] = DFFEAS(data2usb[13]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[14] is data2usb[14] at LC_X19_Y19_N8
--operation mode is normal

data2usb[14]_lut_out = A1L97Q & (C1_q_b[14]) # !A1L97Q & A1L112Q;
data2usb[14] = DFFEAS(data2usb[14]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--data2usb[15] is data2usb[15] at LC_X19_Y19_N4
--operation mode is normal

data2usb[15]_lut_out = A1L97Q & (C1_q_b[15]) # !A1L97Q & A1L113Q;
data2usb[15] = DFFEAS(data2usb[15]_lut_out, GLOBAL(gclk), VCC, , A1L75, , , , );


--A1L240 is LessThan~430 at LC_X21_Y14_N5
--operation mode is arithmetic

A1L240_cout_0 = fifordaddr[5] & (!A1L243 # !fifowraddr[5]) # !fifordaddr[5] & !fifowraddr[5] & !A1L243;
A1L240 = CARRY(A1L240_cout_0);

--A1L241 is LessThan~430COUT1_463 at LC_X21_Y14_N5
--operation mode is arithmetic

A1L241_cout_1 = fifordaddr[5] & (!A1L243 # !fifowraddr[5]) # !fifordaddr[5] & !fifowraddr[5] & !A1L243;
A1L241 = CARRY(A1L241_cout_1);


--C1_q_b[0] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[0] at M4K_X17_Y14
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[0]_PORT_A_data_in = BUS(A1L170, A1L188, A1L191, A1L194);
C1_q_b[0]_PORT_A_data_in_reg = DFFE(C1_q_b[0]_PORT_A_data_in, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[0]_PORT_A_address_reg = DFFE(C1_q_b[0]_PORT_A_address, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[0]_PORT_B_address_reg = DFFE(C1_q_b[0]_PORT_B_address, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_PORT_A_write_enable = VCC;
C1_q_b[0]_PORT_A_write_enable_reg = DFFE(C1_q_b[0]_PORT_A_write_enable, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_read_enable = VCC;
C1_q_b[0]_PORT_B_read_enable_reg = DFFE(C1_q_b[0]_PORT_B_read_enable, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_clock_0 = GLOBAL(gclk);
C1_q_b[0]_clock_1 = GLOBAL(gclk);
C1_q_b[0]_clock_enable_0 = A1L114;
C1_q_b[0]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[0]_PORT_B_data_out = MEMORY(C1_q_b[0]_PORT_A_data_in_reg, , C1_q_b[0]_PORT_A_address_reg, C1_q_b[0]_PORT_B_address_reg, C1_q_b[0]_PORT_A_write_enable_reg, C1_q_b[0]_PORT_B_read_enable_reg, , , C1_q_b[0]_clock_0, C1_q_b[0]_clock_1, C1_q_b[0]_clock_enable_0, C1_q_b[0]_clock_enable_1, , );
C1_q_b[0] = C1_q_b[0]_PORT_B_data_out[0];

--C1_q_b[8] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[8] at M4K_X17_Y14
C1_q_b[0]_PORT_A_data_in = BUS(A1L170, A1L188, A1L191, A1L194);
C1_q_b[0]_PORT_A_data_in_reg = DFFE(C1_q_b[0]_PORT_A_data_in, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[0]_PORT_A_address_reg = DFFE(C1_q_b[0]_PORT_A_address, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[0]_PORT_B_address_reg = DFFE(C1_q_b[0]_PORT_B_address, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_PORT_A_write_enable = VCC;
C1_q_b[0]_PORT_A_write_enable_reg = DFFE(C1_q_b[0]_PORT_A_write_enable, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_read_enable = VCC;
C1_q_b[0]_PORT_B_read_enable_reg = DFFE(C1_q_b[0]_PORT_B_read_enable, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_clock_0 = GLOBAL(gclk);
C1_q_b[0]_clock_1 = GLOBAL(gclk);
C1_q_b[0]_clock_enable_0 = A1L114;
C1_q_b[0]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[0]_PORT_B_data_out = MEMORY(C1_q_b[0]_PORT_A_data_in_reg, , C1_q_b[0]_PORT_A_address_reg, C1_q_b[0]_PORT_B_address_reg, C1_q_b[0]_PORT_A_write_enable_reg, C1_q_b[0]_PORT_B_read_enable_reg, , , C1_q_b[0]_clock_0, C1_q_b[0]_clock_1, C1_q_b[0]_clock_enable_0, C1_q_b[0]_clock_enable_1, , );
C1_q_b[8] = C1_q_b[0]_PORT_B_data_out[3];

--C1_q_b[7] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[7] at M4K_X17_Y14
C1_q_b[0]_PORT_A_data_in = BUS(A1L170, A1L188, A1L191, A1L194);
C1_q_b[0]_PORT_A_data_in_reg = DFFE(C1_q_b[0]_PORT_A_data_in, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[0]_PORT_A_address_reg = DFFE(C1_q_b[0]_PORT_A_address, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[0]_PORT_B_address_reg = DFFE(C1_q_b[0]_PORT_B_address, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_PORT_A_write_enable = VCC;
C1_q_b[0]_PORT_A_write_enable_reg = DFFE(C1_q_b[0]_PORT_A_write_enable, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_read_enable = VCC;
C1_q_b[0]_PORT_B_read_enable_reg = DFFE(C1_q_b[0]_PORT_B_read_enable, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_clock_0 = GLOBAL(gclk);
C1_q_b[0]_clock_1 = GLOBAL(gclk);
C1_q_b[0]_clock_enable_0 = A1L114;
C1_q_b[0]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[0]_PORT_B_data_out = MEMORY(C1_q_b[0]_PORT_A_data_in_reg, , C1_q_b[0]_PORT_A_address_reg, C1_q_b[0]_PORT_B_address_reg, C1_q_b[0]_PORT_A_write_enable_reg, C1_q_b[0]_PORT_B_read_enable_reg, , , C1_q_b[0]_clock_0, C1_q_b[0]_clock_1, C1_q_b[0]_clock_enable_0, C1_q_b[0]_clock_enable_1, , );
C1_q_b[7] = C1_q_b[0]_PORT_B_data_out[2];

--C1_q_b[6] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[6] at M4K_X17_Y14
C1_q_b[0]_PORT_A_data_in = BUS(A1L170, A1L188, A1L191, A1L194);
C1_q_b[0]_PORT_A_data_in_reg = DFFE(C1_q_b[0]_PORT_A_data_in, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[0]_PORT_A_address_reg = DFFE(C1_q_b[0]_PORT_A_address, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[0]_PORT_B_address_reg = DFFE(C1_q_b[0]_PORT_B_address, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_PORT_A_write_enable = VCC;
C1_q_b[0]_PORT_A_write_enable_reg = DFFE(C1_q_b[0]_PORT_A_write_enable, C1_q_b[0]_clock_0, , , C1_q_b[0]_clock_enable_0);
C1_q_b[0]_PORT_B_read_enable = VCC;
C1_q_b[0]_PORT_B_read_enable_reg = DFFE(C1_q_b[0]_PORT_B_read_enable, C1_q_b[0]_clock_1, , , C1_q_b[0]_clock_enable_1);
C1_q_b[0]_clock_0 = GLOBAL(gclk);
C1_q_b[0]_clock_1 = GLOBAL(gclk);
C1_q_b[0]_clock_enable_0 = A1L114;
C1_q_b[0]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[0]_PORT_B_data_out = MEMORY(C1_q_b[0]_PORT_A_data_in_reg, , C1_q_b[0]_PORT_A_address_reg, C1_q_b[0]_PORT_B_address_reg, C1_q_b[0]_PORT_A_write_enable_reg, C1_q_b[0]_PORT_B_read_enable_reg, , , C1_q_b[0]_clock_0, C1_q_b[0]_clock_1, C1_q_b[0]_clock_enable_0, C1_q_b[0]_clock_enable_1, , );
C1_q_b[6] = C1_q_b[0]_PORT_B_data_out[1];


--A1L98Q is fifomemory~4 at LC_X19_Y16_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

A1L98Q_lut_out = GND;
A1L98Q = DFFEAS(A1L98Q_lut_out, GLOBAL(gclk), VCC, , A1L118, A1L170, , , VCC);


--A1L97Q is fifomemory~3 at LC_X16_Y17_N2
--operation mode is normal

A1L97Q_lut_out = VCC;
A1L97Q = DFFEAS(A1L97Q_lut_out, GLOBAL(gclk), GLOBAL(RESETFPGA), , !CTL1_FLAGB, , , , );


--A1L75 is data2usb[0]~15 at LC_X19_Y19_N9
--operation mode is normal

A1L75 = !CTL1_FLAGB & RESETFPGA;


--C1_q_b[1] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[1] at M4K_X17_Y16
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[1]_PORT_A_data_in = BUS(A1L173, A1L179, A1L182, A1L185);
C1_q_b[1]_PORT_A_data_in_reg = DFFE(C1_q_b[1]_PORT_A_data_in, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[1]_PORT_A_address_reg = DFFE(C1_q_b[1]_PORT_A_address, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[1]_PORT_B_address_reg = DFFE(C1_q_b[1]_PORT_B_address, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_PORT_A_write_enable = VCC;
C1_q_b[1]_PORT_A_write_enable_reg = DFFE(C1_q_b[1]_PORT_A_write_enable, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_read_enable = VCC;
C1_q_b[1]_PORT_B_read_enable_reg = DFFE(C1_q_b[1]_PORT_B_read_enable, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_clock_0 = GLOBAL(gclk);
C1_q_b[1]_clock_1 = GLOBAL(gclk);
C1_q_b[1]_clock_enable_0 = A1L114;
C1_q_b[1]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[1]_PORT_B_data_out = MEMORY(C1_q_b[1]_PORT_A_data_in_reg, , C1_q_b[1]_PORT_A_address_reg, C1_q_b[1]_PORT_B_address_reg, C1_q_b[1]_PORT_A_write_enable_reg, C1_q_b[1]_PORT_B_read_enable_reg, , , C1_q_b[1]_clock_0, C1_q_b[1]_clock_1, C1_q_b[1]_clock_enable_0, C1_q_b[1]_clock_enable_1, , );
C1_q_b[1] = C1_q_b[1]_PORT_B_data_out[0];

--C1_q_b[5] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[5] at M4K_X17_Y16
C1_q_b[1]_PORT_A_data_in = BUS(A1L173, A1L179, A1L182, A1L185);
C1_q_b[1]_PORT_A_data_in_reg = DFFE(C1_q_b[1]_PORT_A_data_in, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[1]_PORT_A_address_reg = DFFE(C1_q_b[1]_PORT_A_address, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[1]_PORT_B_address_reg = DFFE(C1_q_b[1]_PORT_B_address, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_PORT_A_write_enable = VCC;
C1_q_b[1]_PORT_A_write_enable_reg = DFFE(C1_q_b[1]_PORT_A_write_enable, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_read_enable = VCC;
C1_q_b[1]_PORT_B_read_enable_reg = DFFE(C1_q_b[1]_PORT_B_read_enable, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_clock_0 = GLOBAL(gclk);
C1_q_b[1]_clock_1 = GLOBAL(gclk);
C1_q_b[1]_clock_enable_0 = A1L114;
C1_q_b[1]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[1]_PORT_B_data_out = MEMORY(C1_q_b[1]_PORT_A_data_in_reg, , C1_q_b[1]_PORT_A_address_reg, C1_q_b[1]_PORT_B_address_reg, C1_q_b[1]_PORT_A_write_enable_reg, C1_q_b[1]_PORT_B_read_enable_reg, , , C1_q_b[1]_clock_0, C1_q_b[1]_clock_1, C1_q_b[1]_clock_enable_0, C1_q_b[1]_clock_enable_1, , );
C1_q_b[5] = C1_q_b[1]_PORT_B_data_out[3];

--C1_q_b[4] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[4] at M4K_X17_Y16
C1_q_b[1]_PORT_A_data_in = BUS(A1L173, A1L179, A1L182, A1L185);
C1_q_b[1]_PORT_A_data_in_reg = DFFE(C1_q_b[1]_PORT_A_data_in, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[1]_PORT_A_address_reg = DFFE(C1_q_b[1]_PORT_A_address, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[1]_PORT_B_address_reg = DFFE(C1_q_b[1]_PORT_B_address, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_PORT_A_write_enable = VCC;
C1_q_b[1]_PORT_A_write_enable_reg = DFFE(C1_q_b[1]_PORT_A_write_enable, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_read_enable = VCC;
C1_q_b[1]_PORT_B_read_enable_reg = DFFE(C1_q_b[1]_PORT_B_read_enable, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_clock_0 = GLOBAL(gclk);
C1_q_b[1]_clock_1 = GLOBAL(gclk);
C1_q_b[1]_clock_enable_0 = A1L114;
C1_q_b[1]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[1]_PORT_B_data_out = MEMORY(C1_q_b[1]_PORT_A_data_in_reg, , C1_q_b[1]_PORT_A_address_reg, C1_q_b[1]_PORT_B_address_reg, C1_q_b[1]_PORT_A_write_enable_reg, C1_q_b[1]_PORT_B_read_enable_reg, , , C1_q_b[1]_clock_0, C1_q_b[1]_clock_1, C1_q_b[1]_clock_enable_0, C1_q_b[1]_clock_enable_1, , );
C1_q_b[4] = C1_q_b[1]_PORT_B_data_out[2];

--C1_q_b[3] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[3] at M4K_X17_Y16
C1_q_b[1]_PORT_A_data_in = BUS(A1L173, A1L179, A1L182, A1L185);
C1_q_b[1]_PORT_A_data_in_reg = DFFE(C1_q_b[1]_PORT_A_data_in, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[1]_PORT_A_address_reg = DFFE(C1_q_b[1]_PORT_A_address, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
C1_q_b[1]_PORT_B_address_reg = DFFE(C1_q_b[1]_PORT_B_address, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_PORT_A_write_enable = VCC;
C1_q_b[1]_PORT_A_write_enable_reg = DFFE(C1_q_b[1]_PORT_A_write_enable, C1_q_b[1]_clock_0, , , C1_q_b[1]_clock_enable_0);
C1_q_b[1]_PORT_B_read_enable = VCC;
C1_q_b[1]_PORT_B_read_enable_reg = DFFE(C1_q_b[1]_PORT_B_read_enable, C1_q_b[1]_clock_1, , , C1_q_b[1]_clock_enable_1);
C1_q_b[1]_clock_0 = GLOBAL(gclk);
C1_q_b[1]_clock_1 = GLOBAL(gclk);
C1_q_b[1]_clock_enable_0 = A1L114;
C1_q_b[1]_clock_enable_1 = !CTL1_FLAGB;
C1_q_b[1]_PORT_B_data_out = MEMORY(C1_q_b[1]_PORT_A_data_in_reg, , C1_q_b[1]_PORT_A_address_reg, C1_q_b[1]_PORT_B_address_reg, C1_q_b[1]_PORT_A_write_enable_reg, C1_q_b[1]_PORT_B_read_enable_reg, , , C1_q_b[1]_clock_0, C1_q_b[1]_clock_1, C1_q_b[1]_clock_enable_0, C1_q_b[1]_clock_enable_1, , );
C1_q_b[3] = C1_q_b[1]_PORT_B_data_out[1];


--A1L99Q is fifomemory~6 at LC_X19_Y16_N0
--operation mode is normal

A1L99Q_lut_out = A1L173;
A1L99Q = DFFEAS(A1L99Q_lut_out, GLOBAL(gclk), VCC, , A1L118, , , , );


--C1_q_b[2] is altsyncram:fifomemory_rtl_0|altsyncram_lk81:auto_generated|q_b[2] at M4K_X17_Y15
--RAM Block Operation Mode: Simple Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 16, Port B Logical Depth: 1024, Port B Logical Width: 16
--Port A Input: Registered, Port B Input: Registered, Port B Output: Un-registered
C1_q_b[2]_PORT_A_data_in = BUS(A1L176, A1L197, A1L206, A1L209);
C1_q_b[2]_PORT_A_data_in_reg = DFFE(C1_q_b[2]_PORT_A_data_in, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_A_address = BUS(fifowraddr[0], fifowraddr[1], fifowraddr[2], fifowraddr[3], fifowraddr[4], fifowraddr[5], fifowraddr[6], fifowraddr[7], fifowraddr[8], fifowraddr[9]);
C1_q_b[2]_PORT_A_address_reg = DFFE(C1_q_b[2]_PORT_A_address, C1_q_b[2]_clock_0, , , C1_q_b[2]_clock_enable_0);
C1_q_b[2]_PORT_B_address = BUS(A1L43, A1L39, A1L55, A1L51, A1L66, A1L47, A1L59, A1L35, A1L63, A1L31);
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