📄 usb_fpga.fit.qmsg
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Web Edition " "Info: Version 5.1 Build 176 10/26/2005 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Oct 30 20:34:42 2007 " "Info: Processing started: Tue Oct 30 20:34:42 2007" { } { } 0 0 "Processing started: %1!s!" 0 0} } { } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off USB_FPGA -c USB_FPGA " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off USB_FPGA -c USB_FPGA" { } { } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "USB_FPGA EP1C6Q240C8 " "Info: Selected device EP1C6Q240C8 for design \"USB_FPGA\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C12Q240C8 " "Info: Device EP1C12Q240C8 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "IFSAC_FSAC_PINS_MISSING_LOCATION_INFO" "39 86 " "Info: No exact pin location assignment(s) for 39 pins of 86 total pins" { { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[0\] " "Info: Pin SRAMFD\[0\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[0] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[1\] " "Info: Pin SRAMFD\[1\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[1] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[2\] " "Info: Pin SRAMFD\[2\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[2] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[3\] " "Info: Pin SRAMFD\[3\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[3] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[4\] " "Info: Pin SRAMFD\[4\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[4] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[5\] " "Info: Pin SRAMFD\[5\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[5] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[6\] " "Info: Pin SRAMFD\[6\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[6] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[7\] " "Info: Pin SRAMFD\[7\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[7] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[8\] " "Info: Pin SRAMFD\[8\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[8] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[9\] " "Info: Pin SRAMFD\[9\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[9] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[10\] " "Info: Pin SRAMFD\[10\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[10] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[11\] " "Info: Pin SRAMFD\[11\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[11] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[12\] " "Info: Pin SRAMFD\[12\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[12] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[13\] " "Info: Pin SRAMFD\[13\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[13] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[14\] " "Info: Pin SRAMFD\[14\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[14] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMFD\[15\] " "Info: Pin SRAMFD\[15\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 38 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMFD\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMFD[15] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMFD[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[0\] " "Info: Pin SRAMADR\[0\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[0\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[0] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[1\] " "Info: Pin SRAMADR\[1\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[1\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[1] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[2\] " "Info: Pin SRAMADR\[2\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[2\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[2] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[3\] " "Info: Pin SRAMADR\[3\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[3\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[3] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[4\] " "Info: Pin SRAMADR\[4\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[4\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[4] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[5\] " "Info: Pin SRAMADR\[5\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[5\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[5] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[6\] " "Info: Pin SRAMADR\[6\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[6\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[6] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[7\] " "Info: Pin SRAMADR\[7\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[7\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[7] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[7] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[8\] " "Info: Pin SRAMADR\[8\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[8\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[8] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[8] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[9\] " "Info: Pin SRAMADR\[9\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[9\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[9] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[9] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[10\] " "Info: Pin SRAMADR\[10\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[10\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[10] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[10] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[11\] " "Info: Pin SRAMADR\[11\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[11\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[11] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[11] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[12\] " "Info: Pin SRAMADR\[12\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[12\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[12] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[12] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[13\] " "Info: Pin SRAMADR\[13\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[13\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[13] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[14\] " "Info: Pin SRAMADR\[14\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[14\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[14] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[14] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[15\] " "Info: Pin SRAMADR\[15\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[15\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[15] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[15] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[16\] " "Info: Pin SRAMADR\[16\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[16\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[16] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[16] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMADR\[17\] " "Info: Pin SRAMADR\[17\] not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 39 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMADR\[17\]" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMADR[17] } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMADR[17] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMWE " "Info: Pin SRAMWE not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 40 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMWE" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMWE } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMWE } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMCE " "Info: Pin SRAMCE not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 41 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMCE" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMCE } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMCE } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMOE " "Info: Pin SRAMOE not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 42 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMOE" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMOE } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMOE } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMUB " "Info: Pin SRAMUB not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 43 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMUB" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMUB } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMUB } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} { "Info" "IFSAC_FSAC_PIN_MISSING_LOCATION_INFO" "SRAMLB " "Info: Pin SRAMLB not assigned to an exact location on the device" { } { { "USB_FPGA.vhd" "" { Text "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.vhd" 44 -1 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "SRAMLB" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "USB_FPGA" "UNKNOWN" "V1" "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/db/USB_FPGA.quartus_db" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/" "" "" { SRAMLB } "NODE_NAME" } "" } } { "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" { Floorplan "G:/光盘/CD1/测试程序源代码/GPIF_FIFO_WR_RD/FPGA/USB_FPGA.fld" "" "" { SRAMLB } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0} } { } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" { } { } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
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